alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | ; Copyright (c) 2021 Arm Limited. All rights reserved. |
| 2 | ; SPDX-License-Identifier: Apache-2.0 |
| 3 | ; |
| 4 | ; Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | ; you may not use this file except in compliance with the License. |
| 6 | ; You may obtain a copy of the License at |
| 7 | ; |
| 8 | ; http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | ; |
| 10 | ; Unless required by applicable law or agreed to in writing, software |
| 11 | ; distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | ; See the License for the specific language governing permissions and |
| 14 | ; limitations under the License. |
| 15 | |
| 16 | ; ************************************************************* |
| 17 | ; *** Scatter-Loading Description File *** |
| 18 | ; ************************************************************* |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 19 | ; Please see docs/sections/appendix.md for memory mapping information. |
| 20 | ; |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 21 | ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR |
| 22 | ; sections => activation buffers and the model should only |
| 23 | ; be placed in those regions. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 24 | ; |
| 25 | ;--------------------------------------------------------- |
| 26 | ; First load region (ITCM) |
| 27 | ;--------------------------------------------------------- |
| 28 | LOAD_REGION_0 0x00000000 0x00080000 |
| 29 | { |
| 30 | ;----------------------------------------------------- |
| 31 | ; First part of code mem - 512kiB |
| 32 | ;----------------------------------------------------- |
| 33 | itcm.bin 0x00000000 0x00080000 |
| 34 | { |
| 35 | *.o (RESET, +First) |
| 36 | * (InRoot$$Sections) |
| 37 | |
| 38 | ; Essentially only RO-CODE, RO-DATA is in a |
| 39 | ; different region. |
| 40 | .ANY (+RO) |
| 41 | } |
| 42 | |
| 43 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 44 | ; 128kiB of 512kiB DTCM is used for any other RW or ZI |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 45 | ; data. Note: this region is internal to the Cortex-M |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 46 | ; CPU. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 47 | ;----------------------------------------------------- |
| 48 | dtcm.bin 0x20000000 0x00020000 |
| 49 | { |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 50 | ; Any R/W and/or zero initialised data |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 51 | .ANY(+RW +ZI) |
| 52 | } |
| 53 | |
| 54 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 55 | ; 384kiB of stack space within the DTCM region. See |
| 56 | ; `dtcm.bin` for the first section. Note: by virtue of |
| 57 | ; being part of DTCM, this region is only accessible |
| 58 | ; from Cortex-M55. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 59 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 60 | ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 61 | {} |
| 62 | |
| 63 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 64 | ; SSE-300's internal SRAM of 2MiB - reserved for |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 65 | ; activation buffers. |
| 66 | ; This region should have 3 cycle read latency from |
Isabella Gottardi | f590773 | 2021-08-06 15:39:41 +0100 | [diff] [blame] | 67 | ; both Cortex-M55 and Ethos-U NPU |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 68 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 69 | isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 70 | { |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 71 | ; Cache area (if used) |
| 72 | *.o (.bss.NoInit.ethos_u_cache) |
| 73 | |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 74 | ; activation buffers a.k.a tensor arena when |
| 75 | ; memory mode sram only or shared sram |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 76 | *.o (.bss.NoInit.activation_buf_sram) |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 77 | } |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | ;--------------------------------------------------------- |
| 81 | ; Second load region (DDR) |
| 82 | ;--------------------------------------------------------- |
| 83 | LOAD_REGION_1 0x70000000 0x02000000 |
| 84 | { |
| 85 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 86 | ; 32 MiB of DDR space for neural network model, |
| 87 | ; input vectors and labels. If the activation buffer |
| 88 | ; size required by the network is bigger than the |
| 89 | ; SRAM size available, it is accommodated here. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 90 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 91 | ddr.bin 0x70000000 ALIGN 16 0x02000000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 92 | { |
| 93 | ; nn model's baked in input matrices |
| 94 | *.o (ifm) |
| 95 | |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 96 | ; nn model's default space |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 97 | *.o (nn_model) |
| 98 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 99 | ; labels |
| 100 | *.o (labels) |
| 101 | |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 102 | ; activation buffers a.k.a tensor arena when memory mode dedicated sram |
| 103 | *.o (activation_buf_dram) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 107 | ; First 256kiB of BRAM (FPGA SRAM) used for RO data. |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 108 | ; Note: Total BRAM size available is 1MiB. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 109 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 110 | bram.bin 0x11000000 ALIGN 8 0x00040000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 111 | { |
| 112 | ; RO data (incl. unwinding tables for debugging) |
| 113 | .ANY (+RO-DATA) |
| 114 | } |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 115 | |
| 116 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 117 | ; 768 KiB of remaining part of the 1MiB BRAM used as |
| 118 | ; heap space. |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 119 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 120 | ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 121 | {} |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 122 | } |