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alexander3c798932021-03-26 21:42:19 +00001/*
Kshitij Sisodiad5679cc2022-03-03 16:30:07 +00002 * Copyright (c) 2022 Arm Limited. All rights reserved.
alexander3c798932021-03-26 21:42:19 +00003 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#include "timer_mps3.h"
18
alexander31ae9f02022-02-10 16:15:54 +000019#include "log_macros.h"
Kshitij Sisodiad5679cc2022-03-03 16:30:07 +000020#include "smm_mps3.h" /* Memory map for MPS3. */
alexander3c798932021-03-26 21:42:19 +000021
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000022static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010023static const char* unit_cycles = "cycles";
24static const char* unit_ms = "milliseconds";
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000025
26/**
27 * @brief Gets the system tick triggered cycle counter for the CPU.
28 * @return 64-bit counter value.
29 **/
30static uint64_t Get_SysTick_Cycle_Count(void);
31
32/**
33 * SysTick initialisation
34 */
35static int Init_SysTick(void);
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010036
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010037/**
38 * @brief Adds one PMU counter to the counters' array
39 * @param value Value of the counter
40 * @param name Name for the given counter
41 * @param unit Unit for the "value"
42 * @param counters Pointer to the counter struct - the one to be populated.
43 * @return true if successfully added, false otherwise
44 */
45static bool add_pmu_counter(
46 uint64_t value,
47 const char* name,
48 const char* unit,
49 pmu_counters* counters);
50
51/**
52 * @brief Gets the evaluated millisecond timestamp from the given MPS3 counter struct.
53 * @param mps3_counters Pointer to the MPS3 counters.
54 * @return microseconds timestamp as 32 bit unsigned integer.
55 */
56static uint32_t get_tstamp_milliseconds(mps3_pmu_counters* mps3_counters);
57
58void platform_reset_counters(void)
alexander3c798932021-03-26 21:42:19 +000059{
60 MPS3_FPGAIO->CLK1HZ = 0;
61 MPS3_FPGAIO->CLK100HZ = 0;
62 MPS3_FPGAIO->COUNTER = 0;
63
64 if (0 != Init_SysTick()) {
65 printf_err("Failed to initialise system tick config\n");
66 }
67 debug("system tick config ready\n");
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010068
69#if defined (ARM_NPU)
70 ethosu_pmu_init();
71#endif /* defined (ARM_NPU) */
alexander3c798932021-03-26 21:42:19 +000072}
73
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010074void platform_get_counters(pmu_counters* counters)
alexander3c798932021-03-26 21:42:19 +000075{
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010076 counters->num_counters = 0;
77 counters->initialised = true;
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010078 uint32_t i = 0;
79
80#if defined (ARM_NPU)
81 ethosu_pmu_counters npu_counters = ethosu_get_pmu_counters();
82 for (i = 0; i < ETHOSU_PMU_NCOUNTERS; ++i) {
83 add_pmu_counter(
84 npu_counters.npu_evt_counters[i].counter_value,
85 npu_counters.npu_evt_counters[i].name,
86 npu_counters.npu_evt_counters[i].unit,
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010087 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010088 }
89 for (i = 0; i < ETHOSU_DERIVED_NCOUNTERS; ++i) {
90 add_pmu_counter(
91 npu_counters.npu_derived_counters[i].counter_value,
92 npu_counters.npu_derived_counters[i].name,
93 npu_counters.npu_derived_counters[i].unit,
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010094 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010095 }
96 add_pmu_counter(
97 npu_counters.npu_total_ccnt,
98 "NPU TOTAL",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010099 unit_cycles,
100 counters);
Kshitij Sisodiaea8ce562022-04-12 11:10:11 +0100101#else
102 UNUSED(i);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100103#endif /* defined (ARM_NPU) */
104
105#if defined(CPU_PROFILE_ENABLED)
106 mps3_pmu_counters mps3_counters = {
107 .counter_1Hz = MPS3_FPGAIO->CLK1HZ,
108 .counter_100Hz = MPS3_FPGAIO->CLK100HZ,
109 .counter_fpga = MPS3_FPGAIO->COUNTER,
110 .counter_systick = Get_SysTick_Cycle_Count()
111 };
112
113 add_pmu_counter(
114 mps3_counters.counter_systick,
115 "CPU TOTAL",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +0100116 unit_cycles,
117 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100118
119 add_pmu_counter(
120 get_tstamp_milliseconds(&mps3_counters),
121 "DURATION",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +0100122 unit_ms,
123 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100124#endif /* defined(CPU_PROFILE_ENABLED) */
125
126#if !defined(CPU_PROFILE_ENABLED)
127 UNUSED(get_tstamp_milliseconds);
128 UNUSED(Get_SysTick_Cycle_Count);
129#if !defined(ARM_NPU)
130 UNUSED(add_pmu_counter);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100131#endif /* !defined(ARM_NPU) */
132#endif /* !defined(CPU_PROFILE_ENABLED) */
alexander3c798932021-03-26 21:42:19 +0000133}
134
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100135uint32_t get_mps3_core_clock(void)
alexander3c798932021-03-26 21:42:19 +0000136{
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100137 const uint32_t default_clock = 32000000 /* 32 MHz clock */;
138 static int warned_once = 0;
139 if (0 != MPS3_SCC->CFG_ACLK) {
140 if (default_clock != MPS3_SCC->CFG_ACLK) {
141 warn("System clock is different to the MPS3 config set clock.\n");
142 }
143 return MPS3_SCC->CFG_ACLK;
alexander3c798932021-03-26 21:42:19 +0000144 }
145
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100146 if (!warned_once) {
147 warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %" PRIu32 "\n",
148 default_clock);
149 warned_once = 1;
alexander3c798932021-03-26 21:42:19 +0000150 }
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100151 return default_clock;
alexander3c798932021-03-26 21:42:19 +0000152}
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000153
154void SysTick_Handler(void)
155{
156 /* Increment the cycle counter based on load value. */
157 cpu_cycle_count += SysTick->LOAD + 1;
158}
159
160/**
161 * Gets the current SysTick derived counter value
162 */
163static uint64_t Get_SysTick_Cycle_Count(void)
164{
165 uint32_t systick_val;
166
167 NVIC_DisableIRQ(SysTick_IRQn);
168 systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk;
169 NVIC_EnableIRQ(SysTick_IRQn);
170
171 return cpu_cycle_count + (SysTick->LOAD - systick_val);
172}
173
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000174
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000175/**
176 * SysTick initialisation
177 */
178static int Init_SysTick(void)
179{
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000180 const uint32_t ticks_10ms = get_mps3_core_clock()/100 + 1;
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000181 int err = 0;
182
183 /* Reset CPU cycle count value. */
184 cpu_cycle_count = 0;
185
186 /* Changing configuration for sys tick => guard from being
187 * interrupted. */
188 NVIC_DisableIRQ(SysTick_IRQn);
189
190 /* SysTick init - this will enable interrupt too. */
191 err = SysTick_Config(ticks_10ms);
192
193 /* Enable interrupt again. */
194 NVIC_EnableIRQ(SysTick_IRQn);
195
196 /* Wait for SysTick to kick off */
197 while (!err && !SysTick->VAL) {
198 __NOP();
199 }
200
201 return err;
202}
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000203
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100204static bool add_pmu_counter(uint64_t value,
205 const char* name,
206 const char* unit,
207 pmu_counters* counters)
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000208{
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100209 const uint32_t idx = counters->num_counters;
210 if (idx < NUM_PMU_COUNTERS) {
211 counters->counters[idx].value = value;
212 counters->counters[idx].name = name;
213 counters->counters[idx].unit = unit;
214 ++counters->num_counters;
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000215
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100216 debug("%s: %" PRIu64 " %s\n", name, value, unit);
217 return true;
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000218 }
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100219 printf_err("Failed to add PMU counter!\n");
220 return false;
221}
222
223static uint32_t get_tstamp_milliseconds(mps3_pmu_counters* mps3_counters)
224{
225 const uint32_t divisor = get_mps3_core_clock() / 1000;
226 if (mps3_counters->counter_100Hz > 100) {
227 return (mps3_counters->counter_100Hz * 10);
228 }
229 return (mps3_counters->counter_systick/divisor);
230}