blob: 884b057ff82f89bbea819a71f86e486dbdfb3e3b [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001;
2; Copyright (c) 2021 Arm Limited. All rights reserved.
3; SPDX-License-Identifier: Apache-2.0
4;
5; Licensed under the Apache License, Version 2.0 (the "License");
6; you may not use this file except in compliance with the License.
7; You may obtain a copy of the License at
8;
9; http://www.apache.org/licenses/LICENSE-2.0
10;
11; Unless required by applicable law or agreed to in writing, software
12; distributed under the License is distributed on an "AS IS" BASIS,
13; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14; See the License for the specific language governing permissions and
15; limitations under the License.
16;
17
18; -----------------------------------------------------------------------------
19; Vela configuration file
20
21; -----------------------------------------------------------------------------
22; System Configuration
23
alexander3c798932021-03-26 21:42:19 +000024; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s)
25[System_Config.Ethos_U55_High_End_Embedded]
26core_clock=500e6
27axi0_port=Sram
28axi1_port=OffChipFlash
29Sram_clock_scale=1.0
30Sram_burst_length=32
31Sram_read_latency=32
32Sram_write_latency=32
33OffChipFlash_clock_scale=0.125
34OffChipFlash_burst_length=128
35OffChipFlash_read_latency=64
36OffChipFlash_write_latency=64
Cisco Cervelleraf085fa52021-08-02 09:32:07 +010037; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s)
38[System_Config.Ethos_U65_High_End]
39core_clock=1e9
40axi0_port=Sram
41axi1_port=Dram
42Sram_clock_scale=1.0
43Sram_burst_length=32
44Sram_read_latency=32
45Sram_write_latency=32
46Dram_clock_scale=0.234375
47Dram_burst_length=128
48Dram_read_latency=500
49Dram_write_latency=250
alexander3c798932021-03-26 21:42:19 +000050; -----------------------------------------------------------------------------
51; Memory Mode
52
alexander3c798932021-03-26 21:42:19 +000053; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
54; The non-SRAM memory is assumed to be read-only
55[Memory_Mode.Shared_Sram]
56const_mem_area=Axi1
57arena_mem_area=Axi0
58cache_mem_area=Axi0
George Gekovbe54c622021-07-06 12:02:26 +010059arena_cache_size=4194304