alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | #---------------------------------------------------------------------------- |
| 2 | # Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | # you may not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
| 16 | #---------------------------------------------------------------------------- |
| 17 | |
| 18 | #---------------------------------------------------------------------------- |
| 19 | # CMake description file for the Ethos-U55 Timing Adapter settings (single |
| 20 | # NPU core with two AXIs). |
| 21 | #---------------------------------------------------------------------------- |
| 22 | |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 23 | set(TA0_BASE "${SEC_ETHOS_U_NPU_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") |
| 24 | set(TA1_BASE "${SEC_ETHOS_U_NPU_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 25 | |
| 26 | message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") |
| 27 | |
| 28 | # Timing adapter settings for AXI0 |
Kshitij Sisodia | 9722fa0 | 2022-05-25 16:57:42 +0100 | [diff] [blame] | 29 | set(TA0_MAXR "16" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") |
| 30 | set(TA0_MAXW "16" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 31 | set(TA0_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") |
| 32 | set(TA0_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") |
| 33 | set(TA0_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") |
| 34 | set(TA0_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") |
| 35 | set(TA0_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") |
| 36 | set(TA0_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") |
| 37 | set(TA0_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") |
| 38 | set(TA0_PERFCNT "0" CACHE STRING "32-bit event counter") |
| 39 | set(TA0_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; |
| 40 | Bit 1: 1=enable random AR reordering (0=default); |
| 41 | Bit 2: 1=enable random R reordering (0=default); |
| 42 | Bit 3: 1=enable random B reordering (0=default); |
| 43 | Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") |
| 44 | set(TA0_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") |
| 45 | set(TA0_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") |
| 46 | |
| 47 | # Timing adapter settings for AXI1 |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 48 | set(TA1_MAXR "24" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") |
Kshitij Sisodia | 9722fa0 | 2022-05-25 16:57:42 +0100 | [diff] [blame] | 49 | set(TA1_MAXW "12" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") |
| 50 | set(TA1_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 51 | set(TA1_RLATENCY "500" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") |
Kshitij Sisodia | 9722fa0 | 2022-05-25 16:57:42 +0100 | [diff] [blame] | 52 | set(TA1_WLATENCY "250" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 53 | set(TA1_PULSE_ON "4000" CACHE STRING "No. of cycles addresses let through (0-65535).") |
Kshitij Sisodia | 9722fa0 | 2022-05-25 16:57:42 +0100 | [diff] [blame] | 54 | set(TA1_PULSE_OFF "1000" CACHE STRING "No. of cycles addresses blocked (0-65535).") |
| 55 | set(TA1_BWCAP "1172" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") |
| 56 | set(TA1_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") |
| 57 | set(TA1_PERFCNT "0" CACHE STRING "32-bit event counter") |
| 58 | set(TA1_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 59 | Bit 1: 1=enable random AR reordering (0=default); |
| 60 | Bit 2: 1=enable random R reordering (0=default); |
| 61 | Bit 3: 1=enable random B reordering (0=default); |
| 62 | Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") |
Kshitij Sisodia | 9722fa0 | 2022-05-25 16:57:42 +0100 | [diff] [blame] | 63 | set(TA1_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") |
| 64 | set(TA1_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") |