blob: dd53a57dab5a39fc1aa77798c35067f09b23f177 [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001; Copyright (c) 2021 Arm Limited. All rights reserved.
2; SPDX-License-Identifier: Apache-2.0
3;
4; Licensed under the Apache License, Version 2.0 (the "License");
5; you may not use this file except in compliance with the License.
6; You may obtain a copy of the License at
7;
8; http://www.apache.org/licenses/LICENSE-2.0
9;
10; Unless required by applicable law or agreed to in writing, software
11; distributed under the License is distributed on an "AS IS" BASIS,
12; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13; See the License for the specific language governing permissions and
14; limitations under the License.
15
16; *************************************************************
17; *** Scatter-Loading Description File ***
18; *************************************************************
19; Please see docs/sections/appendix.md for memory mapping information.
20;
Isabella Gottardif5907732021-08-06 15:39:41 +010021; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
alexander3c798932021-03-26 21:42:19 +000022; the model should only be placed in those regions.
23;
24;---------------------------------------------------------
25; First load region (ITCM)
26;---------------------------------------------------------
27LOAD_REGION_0 0x00000000 0x00080000
28{
29 ;-----------------------------------------------------
30 ; First part of code mem - 512kiB
31 ;-----------------------------------------------------
32 itcm.bin 0x00000000 0x00080000
33 {
34 *.o (RESET, +First)
35 * (InRoot$$Sections)
36
37 ; Essentially only RO-CODE, RO-DATA is in a
38 ; different region.
39 .ANY (+RO)
40 }
41
42 ;-----------------------------------------------------
43 ; 128kiB of 512kiB DTCM is used for any other RW or ZI
44 ; data. Note: this region is internal to the Cortex-M
45 ; CPU.
46 ;-----------------------------------------------------
47 dtcm.bin 0x20000000 0x00020000
48 {
49 ; Any R/W and/or zero initialised data
50 .ANY(+RW +ZI)
51 }
52
53 ;-----------------------------------------------------
54 ; 384kiB of stack space within the DTCM region. See
55 ; `dtcm.bin` for the first section. Note: by virtue of
56 ; being part of DTCM, this region is only accessible
57 ; from Cortex-M55.
58 ;-----------------------------------------------------
59 ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000
60 {}
61
62 ;-----------------------------------------------------
63 ; SSE-300's internal SRAM of 4MiB - reserved for
64 ; activation buffers.
65 ; This region should have 3 cycle read latency from
Isabella Gottardif5907732021-08-06 15:39:41 +010066 ; both Cortex-M55 and Ethos-U NPU
alexander3c798932021-03-26 21:42:19 +000067 ;-----------------------------------------------------
68 isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000
69 {
70 ; activation buffers a.k.a tensor arena
71 *.o (.bss.NoInit.activation_buf)
72 }
73}
74
75;---------------------------------------------------------
76; Second load region (DDR)
77;---------------------------------------------------------
78LOAD_REGION_1 0x70000000 0x02000000
79{
80 ;-----------------------------------------------------
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010081 ; 32 MiB of DDR space for neural network model,
alexander3c798932021-03-26 21:42:19 +000082 ; input vectors and labels. If the activation buffer
83 ; size required by the network is bigger than the
84 ; SRAM size available, it is accommodated here.
85 ;-----------------------------------------------------
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010086 ddr.bin 0x70000000 ALIGN 16 0x02000000
alexander3c798932021-03-26 21:42:19 +000087 {
88 ; nn model's baked in input matrices
89 *.o (ifm)
90
91 ; nn model
92 *.o (nn_model)
93
94 ; labels
95 *.o (labels)
96
97 ; if the activation buffer (tensor arena) doesn't
98 ; fit in the SRAM region, we accommodate it here
99 *.o (activation_buf)
100 }
101
102 ;-----------------------------------------------------
103 ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
104 ; Note: Total BRAM size available is 2MiB.
105 ;-----------------------------------------------------
106 bram.bin 0x11000000 ALIGN 8 0x00040000
107 {
108 ; RO data (incl. unwinding tables for debugging)
109 .ANY (+RO-DATA)
110 }
111
112 ;-----------------------------------------------------
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +0100113 ; 960 KiB of remaining part of the 2MiB BRAM used as
114 ; heap space. 0x000F0000 of 0x0x001C0000 available.
alexander3c798932021-03-26 21:42:19 +0000115 ;-----------------------------------------------------
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +0100116 ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000F0000
alexander3c798932021-03-26 21:42:19 +0000117 {}
118}