alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | #---------------------------------------------------------------------------- |
| 2 | # Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | # you may not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
| 16 | #---------------------------------------------------------------------------- |
| 17 | |
| 18 | # CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design |
| 19 | ################################################################################################### |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 20 | # Mem sizes # |
| 21 | ################################################################################################### |
| 22 | set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") |
| 23 | set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 24 | set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB") |
| 25 | set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB") |
| 26 | set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 27 | set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB") |
| 28 | set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") |
| 29 | |
| 30 | ################################################################################################### |
| 31 | # Base addresses for memory regions # |
| 32 | ################################################################################################### |
| 33 | set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") |
| 34 | set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") |
| 35 | set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") |
| 36 | set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address") |
| 37 | set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address") |
| 38 | set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address") |
| 39 | set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 40 | set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 41 | set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") |
| 42 | set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") |
| 43 | set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") |
| 44 | set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") |
| 45 | set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") |
| 46 | |
| 47 | set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") |
| 48 | set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") |
| 49 | set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") |
| 50 | set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address") |
| 51 | set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address") |
| 52 | set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address") |
| 53 | set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 54 | set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address") |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 55 | set(QSPI_SRAM_BASE_S "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 56 | set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") |
| 57 | set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") |
| 58 | set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") |
| 59 | set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") |
| 60 | |
Kshitij Sisodia | aa5e1f6 | 2021-09-24 14:42:08 +0100 | [diff] [blame] | 61 | ################################################################################################### |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 62 | # Application specific config # |
| 63 | ################################################################################################### |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 64 | set(APP_NOTE "AN552") |
| 65 | set(DESIGN_NAME "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name") |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 66 | |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 67 | # The following parameter is based on the linker/scatter script for SSE-300. |
| 68 | # Do not change this parameter in isolation. |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 69 | # SRAM size reserved for activation buffers |
| 70 | math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) |
| 71 | |
| 72 | ################################################################################################### |
Kshitij Sisodia | aa5e1f6 | 2021-09-24 14:42:08 +0100 | [diff] [blame] | 73 | # Base addresses for dynamic loads (to be used for FVP form only) # |
| 74 | ################################################################################################### |
| 75 | # This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these |
| 76 | # parameters in isolation. |
| 77 | set(DYNAMIC_MODEL_BASE "${DDR4_BLK1_BASE_S}" CACHE STRING |
| 78 | "Region to be used for dynamic load of model into memory") |
| 79 | set(DYNAMIC_MODEL_SIZE "0x02000000" CACHE STRING "Size of the space reserved for the model") |
| 80 | math(EXPR DYNAMIC_IFM_BASE "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL) |
| 81 | set(DYNAMIC_IFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the IFM") |
| 82 | math(EXPR DYNAMIC_OFM_BASE "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL) |
| 83 | set(DYNAMIC_OFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the OFM") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 84 | |
| 85 | ################################################################################################### |
| 86 | # Base addresses for peripherals - non secure # |
| 87 | ################################################################################################### |
| 88 | set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)") |
| 89 | set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)") |
| 90 | set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)") |
| 91 | set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)") |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 92 | set(FMC_CMDSK_GPIO_BASE0 "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)") |
| 93 | set(FMC_CMDSK_GPIO_BASE1 "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)") |
| 94 | set(FMC_CMDSK_GPIO_BASE2 "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)") |
| 95 | set(FMC_USER_AHB_BASE "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)") |
| 96 | set(DMA0_BASE "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)") |
| 97 | set(DMA1_BASE "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)") |
| 98 | set(DMA2_BASE "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)") |
| 99 | set(DMA3_BASE "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 100 | |
| 101 | set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)") |
| 102 | set(USB_BASE "0x41500000" CACHE STRING "USB Base Address (1MB)") |
| 103 | |
| 104 | set(USER_APB0_BASE "0x41700000" CACHE STRING "User APB0") |
| 105 | set(USER_APB1_BASE "0x41701000" CACHE STRING "User APB1") |
| 106 | set(USER_APB2_BASE "0x41702000" CACHE STRING "User APB2") |
| 107 | set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3") |
| 108 | |
| 109 | set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ") |
| 110 | set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ") |
| 111 | |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 112 | if (ETHOS_U_NPU_ENABLED) |
| 113 | set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") |
| 114 | set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") |
| 115 | set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") |
| 116 | endif (ETHOS_U_NPU_ENABLED) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 117 | |
| 118 | set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ") |
| 119 | set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ") |
| 120 | set(MPS3_SSP2_BASE "0x49202000" CACHE STRING "ADC SPI PL022 Base Address") |
| 121 | set(MPS3_SSP3_BASE "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address") |
| 122 | set(MPS3_SSP4_BASE "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address") |
| 123 | set(MPS3_I2C2_BASE "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ") |
| 124 | set(MPS3_I2C3_BASE "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ") |
| 125 | |
| 126 | set(USER_APB_BASE "0x49207000" CACHE STRING "User APB") |
| 127 | set(MPS3_I2C5_BASE "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") |
| 128 | |
| 129 | set(MPS3_SCC_BASE "0x49300000" CACHE STRING "SCC Base Address ") |
| 130 | set(MPS3_AAIC_I2S_BASE "0x49301000" CACHE STRING "Audio Interface I2S Base Address ") |
| 131 | set(MPS3_FPGAIO_BASE "0x49302000" CACHE STRING "FPGA IO Base Address ") |
| 132 | |
| 133 | set(CMSDK_UART0_BASE "0x49303000" CACHE STRING "UART 0 Base Address ") |
| 134 | set(CMSDK_UART1_BASE "0x49304000" CACHE STRING "UART 1 Base Address ") |
| 135 | set(CMSDK_UART2_BASE "0x49305000" CACHE STRING "UART 2 Base Address ") |
| 136 | set(CMSDK_UART3_BASE "0x49306000" CACHE STRING "UART 3 Base Address Shield 0") |
| 137 | set(CMSDK_UART4_BASE "0x49307000" CACHE STRING "UART 4 Base Address Shield 1") |
| 138 | set(CMSDK_UART5_BASE "0x49308000" CACHE STRING "UART 5 Base Address ") |
| 139 | |
| 140 | set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ") |
| 141 | set(RTC_BASE "0x4930B000" CACHE STRING "RTC Base address ") |
| 142 | |
| 143 | ################################################################################################### |
| 144 | # Base addresses for peripherals - secure # |
| 145 | ################################################################################################### |
| 146 | set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)") |
| 147 | set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)") |
| 148 | set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)") |
| 149 | set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)") |
| 150 | |
| 151 | set(SEC_AHB_USER0_BASE "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)") |
| 152 | set(SEC_AHB_USER1_BASE "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)") |
| 153 | set(SEC_AHB_USER2_BASE "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)") |
| 154 | set(SEC_AHB_USER3_BASE "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)") |
| 155 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 156 | set(SEC_DMA0_BASE "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)") |
| 157 | set(SEC_DMA1_BASE "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)") |
| 158 | set(SEC_DMA2_BASE "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)") |
| 159 | set(SEC_DMA3_BASE "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 160 | |
| 161 | set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)") |
| 162 | set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address (1MB)") |
| 163 | |
| 164 | set(SEC_USER_APB0_BASE "0x51700000" CACHE STRING "User APB0 Base Address") |
| 165 | set(SEC_USER_APB1_BASE "0x51701000" CACHE STRING "User APB1 Base Address") |
| 166 | set(SEC_USER_APB2_BASE "0x51702000" CACHE STRING "User APB2 Base Address") |
| 167 | set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address") |
| 168 | |
| 169 | set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ") |
| 170 | set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ") |
| 171 | |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 172 | if (ETHOS_U_NPU_ENABLED) |
| 173 | set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") |
| 174 | set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") |
| 175 | set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") |
| 176 | endif (ETHOS_U_NPU_ENABLED) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 177 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 178 | set(SEC_MPS3_I2C0_BASE "0x59200000" CACHE STRING "Touch Screen I2C Base Address ") |
| 179 | set(SEC_MPS3_I2C1_BASE "0x59201000" CACHE STRING "Audio Interface I2C Base Address ") |
| 180 | set(SEC_MPS3_SSP2_BASE "0x59202000" CACHE STRING "ADC SPI PL022 Base Address") |
| 181 | set(SEC_MPS3_SSP3_BASE "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address") |
| 182 | set(SEC_MPS3_SSP4_BASE "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address") |
| 183 | set(SEC_MPS3_I2C2_BASE "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ") |
| 184 | set(SEC_MPS3_I2C3_BASE "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ") |
| 185 | set(SEC_USER_APB_BASE "0x59207000" CACHE STRING "User APB Base Address") |
| 186 | set(SEC_MPS3_I2C5_BASE "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 187 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 188 | set(SEC_MPS3_SCC_BASE "0x59300000" CACHE STRING "SCC Base Address ") |
| 189 | set(SEC_MPS3_AAIC_I2S_BASE "0x59301000" CACHE STRING "Audio Interface I2S Base Address ") |
| 190 | set(SEC_MPS3_FPGAIO_BASE "0x59302000" CACHE STRING "FPGA IO Base Address ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 191 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 192 | set(SEC_CMSDK_UART0_BASE "0x59303000" CACHE STRING "UART 0 Base Address ") |
| 193 | set(SEC_CMSDK_UART1_BASE "0x59304000" CACHE STRING "UART 1 Base Address ") |
| 194 | set(SEC_CMSDK_UART2_BASE "0x59305000" CACHE STRING "UART 2 Base Address ") |
| 195 | set(SEC_CMSDK_UART3_BASE "0x59306000" CACHE STRING "UART 3 Base Address Shield 0") |
| 196 | set(SEC_CMSDK_UART4_BASE "0x59307000" CACHE STRING "UART 4 Base Address Shield 1") |
| 197 | set(SEC_CMSDK_UART5_BASE "0x59308000" CACHE STRING "UART 5 Base Address ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 198 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 199 | set(SEC_CLCD_CONFIG_BASE "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ") |
| 200 | set(SEC_RTC_BASE "0x5930B000" CACHE STRING "RTC Base address ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 201 | |
| 202 | ################################################################################################### |
| 203 | # MPCs # |
| 204 | ################################################################################################### |
| 205 | set(MPC_ISRAM0_BASE_S "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address") |
| 206 | set(MPC_ISRAM1_BASE_S "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address") |
| 207 | set(MPC_BRAM_BASE_S "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address") |
| 208 | set(MPC_QSPI_BASE_S "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address") |
| 209 | set(MPC_DDR4_BASE_S "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address") |
| 210 | |
| 211 | ################################################################################################### |
| 212 | # IRQ numbers # |
| 213 | ################################################################################################### |
| 214 | set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt") |
| 215 | set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ") |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 216 | set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 217 | set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ") |
| 218 | set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ") |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 219 | set(TIMER2_IRQn " 5" CACHE STRING " TIMER 2 Interrupt ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 220 | set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ") |
| 221 | set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ") |
| 222 | set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ") |
| 223 | set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ") |
| 224 | set(MGMT_PPU_IRQn "14" CACHE STRING " MGMT_PPU" ) |
| 225 | set(SYS_PPU_IRQn "15" CACHE STRING " SYS_PPU" ) |
| 226 | set(CPU0_PPU_IRQn "16" CACHE STRING " CPU0_PPU" ) |
| 227 | set(DEBUG_PPU_IRQn "26" CACHE STRING " DEBUG_PPU" ) |
| 228 | set(TIMER3_AON_IRQn "27" CACHE STRING " TIMER3_AON" ) |
| 229 | set(CPU0CTIIQ0_IRQn "28" CACHE STRING " CPU0CTIIQ0" ) |
| 230 | set(CPU0CTIIQ01_IRQn "29" CACHE STRING " CPU0CTIIQ01" ) |
| 231 | |
Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 232 | set(SYS_TSTAMP_COUNTER_IRQn "32" CACHE STRING " System timestamp counter interrupt ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 233 | set(UARTRX0_IRQn "33" CACHE STRING " UART 0 RX Interrupt ") |
| 234 | set(UARTTX0_IRQn "34" CACHE STRING " UART 0 TX Interrupt ") |
| 235 | set(UARTRX1_IRQn "35" CACHE STRING " UART 1 RX Interrupt ") |
| 236 | set(UARTTX1_IRQn "36" CACHE STRING " UART 1 TX Interrupt ") |
| 237 | set(UARTRX2_IRQn "37" CACHE STRING " UART 2 RX Interrupt ") |
| 238 | set(UARTTX2_IRQn "38" CACHE STRING " UART 2 TX Interrupt ") |
| 239 | set(UARTRX3_IRQn "39" CACHE STRING " UART 3 RX Interrupt ") |
| 240 | set(UARTTX3_IRQn "40" CACHE STRING " UART 3 TX Interrupt ") |
| 241 | set(UARTRX4_IRQn "41" CACHE STRING " UART 4 RX Interrupt ") |
| 242 | set(UARTTX4_IRQn "42" CACHE STRING " UART 4 TX Interrupt ") |
| 243 | set(UART0_IRQn "43" CACHE STRING " UART 0 combined Interrupt ") |
| 244 | set(UART1_IRQn "44" CACHE STRING " UART 1 combined Interrupt ") |
| 245 | set(UART2_IRQn "45" CACHE STRING " UART 2 combined Interrupt ") |
| 246 | set(UART3_IRQn "46" CACHE STRING " UART 3 combined Interrupt ") |
| 247 | set(UART4_IRQn "47" CACHE STRING " UART 4 combined Interrupt ") |
| 248 | set(UARTOVF_IRQn "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ") |
| 249 | set(ETHERNET_IRQn "49" CACHE STRING " Ethernet Interrupt ") |
| 250 | set(I2S_IRQn "50" CACHE STRING " Audio I2S Interrupt ") |
| 251 | set(TSC_IRQn "51" CACHE STRING " Touch Screen Interrupt ") |
| 252 | set(USB_IRQn "52" CACHE STRING " USB Interrupt ") |
| 253 | set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt ") |
| 254 | set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ") |
| 255 | set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ") |
| 256 | |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 257 | if (ETHOS_U_NPU_ENABLED) |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 258 | set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 259 | endif () |
| 260 | |
| 261 | set(GPIO0_IRQn "69" CACHE STRING " GPIO 0 Combined Interrupt ") |
| 262 | set(GPIO1_IRQn "70" CACHE STRING " GPIO 1 Combined Interrupt ") |
| 263 | set(GPIO2_IRQn "71" CACHE STRING " GPIO 2 Combined Interrupt ") |
| 264 | set(GPIO3_IRQn "72" CACHE STRING " GPIO 3 Combined Interrupt ") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 265 | set(GPIO0_0_IRQn "73" CACHE STRING "") |
| 266 | set(GPIO0_1_IRQn "74" CACHE STRING "") |
| 267 | set(GPIO0_2_IRQn "75" CACHE STRING "") |
| 268 | set(GPIO0_3_IRQn "76" CACHE STRING "") |
| 269 | set(GPIO0_4_IRQn "77" CACHE STRING "") |
| 270 | set(GPIO0_5_IRQn "78" CACHE STRING "") |
| 271 | set(GPIO0_6_IRQn "79" CACHE STRING "") |
| 272 | set(GPIO0_7_IRQn "80" CACHE STRING "") |
| 273 | set(GPIO0_8_IRQn "81" CACHE STRING "") |
| 274 | set(GPIO0_9_IRQn "82" CACHE STRING "") |
| 275 | set(GPIO0_10_IRQn "83" CACHE STRING "") |
| 276 | set(GPIO0_11_IRQn "84" CACHE STRING "") |
| 277 | set(GPIO0_12_IRQn "85" CACHE STRING "") |
| 278 | set(GPIO0_13_IRQn "86" CACHE STRING "") |
| 279 | set(GPIO0_14_IRQn "87" CACHE STRING "") |
| 280 | set(GPIO0_15_IRQn "88" CACHE STRING "") |
| 281 | set(GPIO1_0_IRQn "89" CACHE STRING "") |
| 282 | set(GPIO1_1_IRQn "90" CACHE STRING "") |
| 283 | set(GPIO1_2_IRQn "91" CACHE STRING "") |
| 284 | set(GPIO1_3_IRQn "92" CACHE STRING "") |
| 285 | set(GPIO1_4_IRQn "93" CACHE STRING "") |
| 286 | set(GPIO1_5_IRQn "94" CACHE STRING "") |
| 287 | set(GPIO1_6_IRQn "95" CACHE STRING "") |
| 288 | set(GPIO1_7_IRQn "96" CACHE STRING "") |
| 289 | set(GPIO1_8_IRQn "97" CACHE STRING "") |
| 290 | set(GPIO1_9_IRQn "98" CACHE STRING "") |
| 291 | set(GPIO1_10_IRQn "99" CACHE STRING "") |
| 292 | set(GPIO1_11_IRQn "100" CACHE STRING "") |
| 293 | set(GPIO1_12_IRQn "101" CACHE STRING "") |
| 294 | set(GPIO1_13_IRQn "102" CACHE STRING "") |
| 295 | set(GPIO1_14_IRQn "103" CACHE STRING "") |
| 296 | set(GPIO1_15_IRQn "104" CACHE STRING "") |
| 297 | set(GPIO2_0_IRQn "105" CACHE STRING "") |
| 298 | set(GPIO2_1_IRQn "106" CACHE STRING "") |
| 299 | set(GPIO2_2_IRQn "107" CACHE STRING "") |
| 300 | set(GPIO2_3_IRQn "108" CACHE STRING "") |
| 301 | set(GPIO2_4_IRQn "109" CACHE STRING "") |
| 302 | set(GPIO2_5_IRQn "110" CACHE STRING "") |
| 303 | set(GPIO2_6_IRQn "111" CACHE STRING "") |
| 304 | set(GPIO2_7_IRQn "112" CACHE STRING "") |
| 305 | set(GPIO2_8_IRQn "113" CACHE STRING "") |
| 306 | set(GPIO2_9_IRQn "114" CACHE STRING "") |
| 307 | set(GPIO2_10_IRQn "115" CACHE STRING "") |
| 308 | set(GPIO2_11_IRQn "116" CACHE STRING "") |
| 309 | set(GPIO2_12_IRQn "117" CACHE STRING "") |
| 310 | set(GPIO2_13_IRQn "118" CACHE STRING "") |
| 311 | set(GPIO2_14_IRQn "119" CACHE STRING "") |
| 312 | set(GPIO2_15_IRQn "120" CACHE STRING "") |
| 313 | set(GPIO3_0_IRQn "121" CACHE STRING "") |
| 314 | set(GPIO3_1_IRQn "122" CACHE STRING "") |
| 315 | set(GPIO3_2_IRQn "123" CACHE STRING "") |
| 316 | set(GPIO3_3_IRQn "124" CACHE STRING "") |
| 317 | set(UARTRX5_IRQn "125" CACHE STRING "UART 5 RX Interrupt") |
| 318 | set(UARTTX5_IRQn "126" CACHE STRING "UART 5 TX Interrupt") |
| 319 | set(UART5_IRQn "127" CACHE STRING "UART 5 combined Interrupt") |