alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 17 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 18 | #include "platform_drivers.h" |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 19 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 20 | #include "log_macros.h" /* Logging functions */ |
Kshitij Sisodia | acc6b85 | 2022-03-01 10:23:11 +0000 | [diff] [blame] | 21 | #include "uart_stdout.h" /* stdout over UART. */ |
Kshitij Sisodia | c22e80e | 2022-03-14 09:26:48 +0000 | [diff] [blame] | 22 | #include "smm_mps3.h" /* Memory map for MPS3. */ |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 23 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 24 | #include <string.h> /* For strncpy */ |
| 25 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 26 | #if defined(ARM_NPU) |
| 27 | #include "ethosu_npu_init.h" |
| 28 | |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 29 | #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 30 | #include "ethosu_ta_init.h" |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 31 | #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 32 | |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 33 | #if defined(ETHOS_U_BASE_ADDR) |
| 34 | #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) |
| 35 | #error "NPU component configured with incorrect NPU base address." |
| 36 | #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */ |
| 37 | #else |
| 38 | #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component." |
| 39 | #endif /* defined(ETHOS_U_BASE_ADDR) */ |
| 40 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 41 | #endif /* ARM_NPU */ |
| 42 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 43 | /** |
| 44 | * @brief Checks if the platform is valid by checking |
| 45 | * the CPU ID for the FPGA implementation against |
| 46 | * the register from the CPU core. |
| 47 | * @return 0 if successful, 1 otherwise |
| 48 | */ |
| 49 | static int verify_platform(void); |
| 50 | |
Kshitij Sisodia | 4cc4021 | 2022-04-08 09:54:53 +0100 | [diff] [blame] | 51 | /** Platform name */ |
| 52 | static const char* s_platform_name = DESIGN_NAME; |
| 53 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 54 | int platform_init(void) |
| 55 | { |
| 56 | int err = 0; |
| 57 | |
| 58 | SystemCoreClockUpdate(); /* From start up code */ |
| 59 | |
| 60 | /* UART init - will enable valid use of printf (stdout |
| 61 | * re-directed at this UART (UART0) */ |
| 62 | UartStdOutInit(); |
| 63 | |
| 64 | if (0 != (err = verify_platform())) { |
| 65 | return err; |
| 66 | } |
| 67 | |
Kshitij Sisodia | ff57034 | 2022-06-10 17:19:22 +0100 | [diff] [blame^] | 68 | #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) |
| 69 | info("Enabling I-cache.\n"); |
| 70 | SCB_EnableICache(); |
| 71 | #endif /* __ICACHE_PRESENT */ |
| 72 | |
| 73 | #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 74 | info("Enabling D-cache.\n"); |
| 75 | SCB_EnableDCache(); |
| 76 | #endif /* __DCACHE_PRESENT */ |
| 77 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 78 | #if defined(ARM_NPU) |
| 79 | |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 80 | #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 81 | /* If the platform has timing adapter blocks along with Ethos-U core |
| 82 | * block, initialise them here. */ |
Kshitij Sisodia | c22e80e | 2022-03-14 09:26:48 +0000 | [diff] [blame] | 83 | if (0 != (err = arm_ethosu_timing_adapter_init())) { |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 84 | return err; |
| 85 | } |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 86 | #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 87 | |
| 88 | int state; |
| 89 | |
| 90 | /* If Arm Ethos-U NPU is to be used, we initialise it here */ |
Kshitij Sisodia | c22e80e | 2022-03-14 09:26:48 +0000 | [diff] [blame] | 91 | if (0 != (state = arm_ethosu_npu_init())) { |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 92 | return state; |
| 93 | } |
| 94 | |
| 95 | #endif /* ARM_NPU */ |
| 96 | |
| 97 | /* Print target design info */ |
Kshitij Sisodia | 4cc4021 | 2022-04-08 09:54:53 +0100 | [diff] [blame] | 98 | info("Target system design: %s\n", s_platform_name); |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | void platform_release(void) |
| 103 | { |
| 104 | __disable_irq(); |
| 105 | } |
| 106 | |
Kshitij Sisodia | 4cc4021 | 2022-04-08 09:54:53 +0100 | [diff] [blame] | 107 | const char* platform_name(void) |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 108 | { |
Kshitij Sisodia | 4cc4021 | 2022-04-08 09:54:53 +0100 | [diff] [blame] | 109 | return s_platform_name; |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 112 | #define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb)) |
| 113 | #define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb)) |
| 114 | #define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb)) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 115 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 116 | static int verify_platform(void) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 117 | { |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 118 | uint32_t id = 0; |
| 119 | uint32_t fpgaid = 0; |
| 120 | uint32_t apnote = 0; |
| 121 | uint32_t rev = 0; |
| 122 | uint32_t aid = 0; |
| 123 | uint32_t fpga_clk = 0; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 124 | const uint32_t ascii_A = (uint32_t)('A'); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 125 | |
| 126 | /* Initialise the LEDs as the switches are */ |
| 127 | MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF; |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 128 | |
Kshitij Sisodia | c22e80e | 2022-03-14 09:26:48 +0000 | [diff] [blame] | 129 | info("Processor internal clock: %" PRIu32 "Hz\n", get_mps3_core_clock()); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 130 | |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 131 | /* Get revision information from various registers */ |
| 132 | rev = MPS3_SCC->CFG_REG4; |
| 133 | fpgaid = MPS3_SCC->SCC_ID; |
| 134 | aid = MPS3_SCC->SCC_AID; |
| 135 | apnote = EXTRACT_BITS(fpgaid, 15, 4); |
Kshitij Sisodia | c22e80e | 2022-03-14 09:26:48 +0000 | [diff] [blame] | 136 | fpga_clk = get_mps3_core_clock(); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 137 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 138 | info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A)); |
| 139 | info("Application Note AN%" PRIx32 ", Revision %c\n", apnote, |
| 140 | (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A)); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 141 | info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24)); |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 142 | info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 143 | |
| 144 | /* Display CPU ID */ |
| 145 | id = SCB->CPUID; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 146 | info("CPU ID: 0x%08" PRIx32 "\n", id); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 147 | |
| 148 | if(EXTRACT_BITS(id, 15, 8) == 0xD2) { |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 149 | if (EXTRACT_BITS(id, 7, 4) == 3) { |
| 150 | info ("CPU: Cortex-M85 r%dp%d\n\n", |
| 151 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 152 | /* @TODO: Remove CPU_CORTEX_M55 from here once CMake min version is > 3.21.0 or when |
| 153 | * toolchains officially support Cortex-M85. Currently, for CMake versions older than |
| 154 | * this, Cortex-M85 is built using Cortex-M55 flags. */ |
| 155 | #if defined (CPU_CORTEX_M55) || defined (ARMv81MML_DSP_DP_MVE_FP) || defined(CPU_CORTEX_M85) |
| 156 | /* CPU ID should be "0x_41_0f_d2_30" for Cortex-M85 */ |
| 157 | return 0; |
| 158 | #endif /* (CPU_CORTEX_M55) || (ARMv81MML_DSP_DP_MVE_FP) || (CPU_CORTEX_M85) */ |
| 159 | } else if (EXTRACT_BITS(id, 7, 4) == 2) { |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 160 | info ("CPU: Cortex-M55 r%dp%d\n\n", |
| 161 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 162 | #if defined (CPU_CORTEX_M55) |
| 163 | /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */ |
| 164 | return 0; |
| 165 | #endif /* CPU_CORTEX_M55 */ |
| 166 | } else if (EXTRACT_BITS(id, 7, 4) == 1) { |
| 167 | info ("CPU: Cortex-M33 r%dp%d\n\n", |
| 168 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 169 | #if defined (CPU_CORTEX_M33) |
| 170 | return 0; |
| 171 | #endif /* CPU_CORTEX_M33 */ |
| 172 | } else if (EXTRACT_BITS(id, 7, 4) == 0) { |
| 173 | info ("CPU: Cortex-M23 r%dp%d\n\n", |
| 174 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 175 | } else { |
| 176 | info ("CPU: Cortex-M processor family"); |
| 177 | } |
| 178 | } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) { |
| 179 | info ("CPU: Cortex-M%d+ r%dp%d\n\n", |
| 180 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 181 | EXTRACT_BITS(id, 3, 0)); |
| 182 | } else { |
| 183 | info ("CPU: Cortex-M%d r%dp%d\n\n", |
| 184 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 185 | EXTRACT_BITS(id, 3, 0)); |
| 186 | } |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 187 | |
| 188 | /* If the CPU is anything other than M33 or M55, we return 1 */ |
| 189 | printf_err("CPU mismatch!\n"); |
| 190 | return 1; |
| 191 | } |