Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 1 | /* |
Kshitij Sisodia | 5385a64 | 2024-01-17 13:29:43 +0000 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates |
| 3 | * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | #ifndef PERIPHERAL_MEMMAP_H |
| 19 | #define PERIPHERAL_MEMMAP_H |
| 20 | |
| 21 | #define DESIGN_NAME "Arm Corstone-300 - AN552" |
| 22 | |
| 23 | /******************************************************************************/ |
| 24 | /* Peripheral memory map */ |
| 25 | /******************************************************************************/ |
| 26 | |
| 27 | #define CMSDK_GPIO0_BASE (0x41100000) /* User GPIO 0 Base Address */ |
| 28 | #define CMSDK_GPIO1_BASE (0x41101000) /* User GPIO 1 Base Address */ |
| 29 | #define CMSDK_GPIO2_BASE (0x41102000) /* User GPIO 2 Base Address */ |
| 30 | #define CMSDK_GPIO3_BASE (0x41103000) /* User GPIO 3 Base Address */ |
| 31 | |
| 32 | #define FMC_CMDSK_GPIO_BASE0 (0x41104000) /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */ |
| 33 | #define FMC_CMDSK_GPIO_BASE1 (0x41105000) /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/ |
| 34 | #define FMC_CMDSK_GPIO_BASE2 (0x41106000) /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/ |
| 35 | #define FMC_USER_AHB_BASE (0x41107000) /* FMC_USER_AHB_BASE Base Address (4KB)*/ |
| 36 | |
Liam Barry | 1b08a52 | 2024-01-30 13:44:09 +0000 | [diff] [blame] | 37 | /* Note: DMA0_BASE does not exist for Corstone-300 */ |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 38 | #define DMA1_BASE (0x41201000) /* DMA1 (4KB) */ |
| 39 | #define DMA2_BASE (0x41202000) /* DMA2 (4KB) */ |
| 40 | #define DMA3_BASE (0x41203000) /* DMA3 (4KB) */ |
| 41 | |
| 42 | #define USER_APB0_BASE (0x41700000) /* User APB0 */ |
| 43 | #define USER_APB1_BASE (0x41701000) /* User APB1 */ |
| 44 | #define USER_APB2_BASE (0x41702000) /* User APB2 */ |
| 45 | #define USER_APB3_BASE (0x41703000) /* User APB3 */ |
| 46 | |
| 47 | #define MPS3_I2C0_BASE (0x49200000) /* Touch Screen I2C Base Address */ |
| 48 | #define MPS3_I2C1_BASE (0x49201000) /* Audio Interface I2C Base Address */ |
| 49 | #define MPS3_SSP2_BASE (0x49202000) /* ADC SPI PL022 Base Address */ |
| 50 | #define MPS3_SSP3_BASE (0x49203000) /* Shield 0 SPI PL022 Base Address */ |
| 51 | |
| 52 | #define MPS3_SSP4_BASE (0x49204000) /* Shield 1 SPI PL022 Base Address */ |
| 53 | #define MPS3_I2C2_BASE (0x49205000) /* Shield 0 SBCon Base Address */ |
| 54 | #define MPS3_I2C3_BASE (0x49206000) /* Shield 1 SBCon Base Address */ |
| 55 | |
| 56 | #define USER_APB_BASE (0x49207000) /* User APB Base Address */ |
| 57 | /* #undef MPS3_I2C4_BASE */ |
| 58 | #define MPS3_I2C5_BASE (0x49208000) /* DDR EPROM I2C SBCon Base Address */ |
| 59 | #define MPS3_SCC_BASE (0x49300000) /* SCC Base Address */ |
| 60 | #define MPS3_AAIC_I2S_BASE (0x49301000) /* Audio Interface I2S Base Address */ |
| 61 | #define MPS3_FPGAIO_BASE (0x49302000) /* FPGA IO Base Address */ |
| 62 | /* #undef PL011_UART0_BASE */ |
| 63 | #define CMSDK_UART0_BASE (0x49303000) /* UART 0 Base Address */ |
| 64 | #define CMSDK_UART1_BASE (0x49304000) /* UART 1 Base Address */ |
| 65 | #define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */ |
| 66 | #define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/ |
| 67 | |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 68 | #define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/ |
| 69 | #define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */ |
| 70 | /* #undef HDMI_AUDIO_BASE */ |
| 71 | #define CLCD_CONFIG_BASE (0x4930A000) /* CLCD CONFIG Base Address */ |
| 72 | #define RTC_BASE (0x4930B000) /* RTC Base address */ |
| 73 | #define SMSC9220_BASE (0x41400000) /* Ethernet SMSC9220 Base Address */ |
| 74 | #define USB_BASE (0x41500000) /* USB Base Address */ |
| 75 | /* #undef CMSDK_SDIO_BASE */ |
| 76 | /* #undef MPS3_CLCD_BASE */ |
| 77 | /* #undef MPS3_eMMC_BASE */ |
| 78 | /* #undef USER_BASE */ |
| 79 | |
| 80 | #define QSPI_XIP_BASE (0x41800000) /* QSPI XIP config Base Address */ |
| 81 | #define QSPI_WRITE_BASE (0x41801000) /* QSPI write config Base Address */ |
| 82 | |
| 83 | /******************************************************************************/ |
| 84 | /* Secure Peripheral memory map */ |
| 85 | /******************************************************************************/ |
| 86 | |
| 87 | #define MPC_ISRAM0_BASE_S (0x50083000) /* ISRAM0 Memory Protection Controller Secure base address */ |
| 88 | #define MPC_ISRAM1_BASE_S (0x50084000) /* ISRAM1 Memory Protection Controller Secure base address */ |
| 89 | |
| 90 | #define SEC_CMSDK_GPIO0_BASE (0x51100000) /* User GPIO 0 Base Address */ |
| 91 | #define SEC_CMSDK_GPIO1_BASE (0x51101000) /* User GPIO 0 Base Address */ |
| 92 | #define SEC_CMSDK_GPIO2_BASE (0x51102000) /* User GPIO 0 Base Address */ |
| 93 | #define SEC_CMSDK_GPIO3_BASE (0x51103000) /* User GPIO 0 Base Address */ |
| 94 | |
| 95 | #define SEC_AHB_USER0_BASE (0x51104000) /* AHB USER 0 Base Address (4KB) */ |
| 96 | #define SEC_AHB_USER1_BASE (0x51105000) /* AHB USER 1 Base Address (4KB)*/ |
| 97 | #define SEC_AHB_USER2_BASE (0x51106000) /* AHB USER 2 Base Address (4KB)*/ |
| 98 | #define SEC_AHB_USER3_BASE (0x51107000) /* AHB USER 3 Base Address (4KB)*/ |
| 99 | |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 100 | #define SEC_DMA1_BASE (0x51201000) /* DMA1 (4KB) */ |
| 101 | #define SEC_DMA2_BASE (0x51202000) /* DMA2 (4KB) */ |
| 102 | #define SEC_DMA3_BASE (0x51203000) /* DMA3 (4KB) */ |
| 103 | |
| 104 | #define SEC_USER_APB0_BASE (0x51700000) /* User APB0 */ |
| 105 | #define SEC_USER_APB1_BASE (0x51701000) /* User APB1 */ |
| 106 | #define SEC_USER_APB2_BASE (0x51702000) /* User APB2 */ |
| 107 | #define SEC_USER_APB3_BASE (0x51703000) /* User APB3 */ |
| 108 | |
| 109 | #define SEC_MPS3_I2C0_BASE (0x59200000) /* Touch Screen I2C Base Address */ |
| 110 | #define SEC_MPS3_I2C1_BASE (0x59201000) /* Audio Interface I2C Base Address */ |
| 111 | #define SEC_MPS3_SSP2_BASE (0x59202000) /* ADC SPI PL022 Base Address */ |
| 112 | #define SEC_MPS3_SSP3_BASE (0x59203000) /* Shield 0 SPI PL022 Base Address */ |
| 113 | |
| 114 | #define SEC_MPS3_SSP4_BASE (0x59204000) /* Shield 1 SPI PL022 Base Address */ |
| 115 | #define SEC_MPS3_I2C2_BASE (0x59205000) /* Shield 0 SBCon Base Address */ |
| 116 | #define SEC_MPS3_I2C3_BASE (0x59206000) /* Shield 1 SBCon Base Address */ |
| 117 | |
| 118 | /* #undef SEC_MPS3_I2C4_BASE */ |
| 119 | #define SEC_MPS3_I2C5_BASE (0x59208000) /* DDR EPROM I2C SBCon Base Address */ |
| 120 | #define SEC_MPS3_SCC_BASE (0x59300000) /* SCC Base Address */ |
| 121 | #define SEC_MPS3_AAIC_I2S_BASE (0x59301000) /* Audio Interface I2S Base Address */ |
| 122 | #define SEC_MPS3_FPGAIO_BASE (0x59302000) /* FPGA IO Base Address */ |
| 123 | #define SEC_CMSDK_UART0_BASE (0x59303000) /* UART 0 Base Address */ |
| 124 | #define SEC_CMSDK_UART1_BASE (0x59304000) /* UART 1 Base Address */ |
| 125 | #define SEC_CMSDK_UART2_BASE (0x59305000) /* UART 2 Base Address */ |
| 126 | #define SEC_CMSDK_UART3_BASE (0x59306000) /* UART 3 Base Address Shield 0*/ |
| 127 | |
| 128 | #define SEC_CMSDK_UART4_BASE (0x59307000) /* UART 4 Base Address Shield 1*/ |
| 129 | #define SEC_CMSDK_UART5_BASE (0x59308000) /* UART 5 Base Address */ |
| 130 | /* #undef SEC_HDMI_AUDIO_BASE */ |
| 131 | #define SEC_CLCD_CONFIG_BASE (0x5930A000) /* CLCD CONFIG Base Address */ |
| 132 | #define SEC_RTC_BASE (0x5930B000) /* RTC Base address */ |
| 133 | #define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC9220 Base Address */ |
| 134 | #define SEC_USB_BASE (0x51500000) /* USB Base Address */ |
| 135 | |
Kshitij Sisodia | 8bc863d | 2022-03-24 17:53:34 +0000 | [diff] [blame] | 136 | /* #undef SEC_USER_BASE */ |
| 137 | |
| 138 | #define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */ |
| 139 | #define SEC_QSPI_WRITE_BASE (0x51801000) /* QSPI write config Base Address */ |
| 140 | |
| 141 | /******************************************************************************/ |
| 142 | /* MPCs */ |
| 143 | /******************************************************************************/ |
| 144 | |
| 145 | #define MPC_ISRAM0_BASE_S (0x50083000) /* Internal SRAM 0 MPC */ |
| 146 | #define MPC_ISRAM1_BASE_S (0x50084000) /* Internal SRAM 1 MPC */ |
| 147 | #define MPC_BRAM_BASE_S (0x57000000) /* SRAM Memory Protection Controller Secure base address */ |
| 148 | #define MPC_QSPI_BASE_S (0x57001000) /* QSPI Memory Protection Controller Secure base address */ |
| 149 | #define MPC_DDR4_BASE_S (0x57002000) /* DDR4 Memory Protection Controller Secure base address */ |
| 150 | |
| 151 | #endif /* PERIPHERAL_MEMMAP_H */ |