commit 3a4785772a0f076e2e9653ad70dbb2fc412ac302
author Kevin Cheng <kevin.cheng@arm.com> Fri Jan 22 17:21:02 2021 -0800
committer Kevin Cheng <kevin.cheng@arm.com> Mon Feb 01 14:19:58 2021 -0800
tree 5260a30572f8359421a410ba4f2cc7512e1e773c
parent e2e13cda4c71f9d72935107bbea9a97df779e347

Remove AINT8

- Updated C and Py serialization libraries, updated licence files
- Removed AINT8 from TOSA reference tests

Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Signed-off-by: Jared Smolens <jared.smolens@arm.com>
Change-Id: I860bfeaad5a075e50f569c8f6861927ebacf1378

reference_model/src/ops/ewise_binary.cc

diff --git a/reference_model/src/ops/ewise_binary.cc b/reference_model/src/ops/ewise_binary.cc
index d07790e..7ed8374 100644
--- a/reference_model/src/ops/ewise_binary.cc
+++ b/reference_model/src/ops/ewise_binary.cc
@@ -1,5 +1,5 @@
 
-// Copyright (c) 2020, ARM Limited.
+// Copyright (c) 2020-2021, ARM Limited.
 //
 //    Licensed under the Apache License, Version 2.0 (the "License");
 //    you may not use this file except in compliance with the License.
@@ -251,7 +251,7 @@
 {
     switch (Dtype)
     {
-        case DType_AINT8:
+        case DType_INT8:
         case DType_INT16:
         case DType_INT32:
             this->fcn = [](InEigenType a, InEigenType b) -> OutEigenType { return a & b; };
@@ -268,7 +268,7 @@
 {
     switch (Dtype)
     {
-        case DType_AINT8:
+        case DType_INT8:
         case DType_INT16:
         case DType_INT32:
             this->fcn = [](InEigenType a, InEigenType b) -> OutEigenType { return a | b; };
@@ -285,7 +285,7 @@
 {
     switch (Dtype)
     {
-        case DType_AINT8:
+        case DType_INT8:
         case DType_INT16:
         case DType_INT32:
             this->fcn = [](InEigenType a, InEigenType b) -> OutEigenType { return a ^ b; };
@@ -567,15 +567,15 @@
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpArithmeticRightShift, INT16);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpArithmeticRightShift, INT32);
 
-DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseAnd, AINT8);
+DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseAnd, INT8);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseAnd, INT16);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseAnd, INT32);
 
-DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseOr, AINT8);
+DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseOr, INT8);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseOr, INT16);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseOr, INT32);
 
-DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseXor, AINT8);
+DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseXor, INT8);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseXor, INT16);
 DEF_INSTANTIATE_RANK0_6_ONE_RANK_ONE_TYPE(OpBitwiseXor, INT32);