commit 47315e1af6947dd93729c6dbd034c7db1af7f312
author Kevin Cheng <kevin.cheng@arm.com> Thu May 13 17:41:28 2021 -0700
committer Kevin Cheng <kevin.cheng@arm.com> Thu May 13 17:41:28 2021 -0700
tree 9ec52894ab993a225a95838d0501db8fefcfb420
parent 14d7f7a2b5d0d85b83d8c84a5456828feb1a0ea1

Fix typo in DIV unit test generator

Change-Id: Id253b62af906a7ffbdbc0d338b6ec92d3795d1c6

verif/tosa_test_gen.py

diff --git a/verif/tosa_test_gen.py b/verif/tosa_test_gen.py
index bc97f15..5670d1b 100644
--- a/verif/tosa_test_gen.py
+++ b/verif/tosa_test_gen.py
@@ -1723,7 +1723,7 @@
 
             # Two invalid cases for Op.DIV:
             # 1. divisor == 0
-            # 2. dividend == (1<<31) and divisor == -1
+            # 2. dividend == -(1<<31) and divisor == -1
             while True:
                 dividend_arr = self.getRandTensor(shapeList[0], dtypeList[0])
                 divisor_arr = self.getRandTensor(shapeList[1], dtypeList[1])
@@ -1731,7 +1731,7 @@
                 if (divisor_arr == 0).any():
                     continue
 
-                if (dividend_arr == (2 ** 31)).any() and (divisor_arr == -1).any():
+                if (dividend_arr == -(2 ** 31)).any() and (divisor_arr == -1).any():
                     continue
 
                 break