Fix logical right shift operator for signed negative integers
The issue reported from https://jira.arm.com/browse/MLTOSA-688
Signed-off-by: Won Jeon <won.jeon@arm.com>
Change-Id: Id37100ba8bc2ac64b1f54788c6f765fedfab0816
diff --git a/reference_model/src/ops/ewise_binary.cc b/reference_model/src/ops/ewise_binary.cc
index c697db0..57eab5f 100644
--- a/reference_model/src/ops/ewise_binary.cc
+++ b/reference_model/src/ops/ewise_binary.cc
@@ -327,21 +327,21 @@
this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType {
REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]",
(int32_t)b);
- return static_cast<OutEigenType>(static_cast<int8_t>(a) >> b);
+ return static_cast<OutEigenType>(static_cast<int8_t>(static_cast<uint8_t>(a) >> b));
};
break;
case DType_INT16:
this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType {
REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]",
(int32_t)b);
- return static_cast<OutEigenType>(static_cast<int16_t>(a) >> b);
+ return static_cast<OutEigenType>(static_cast<int16_t>(static_cast<uint16_t>(a) >> b));
};
break;
case DType_INT32:
this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType {
REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]",
(int32_t)b);
- return static_cast<OutEigenType>(static_cast<int32_t>(a) >> b);
+ return static_cast<OutEigenType>(static_cast<int32_t>(static_cast<uint32_t>(a) >> b));
};
break;
default: