commit ab905ec865a9f4889e6818ce1c4bc934cff2070d
author Matthew Haddon <matthew.haddon@arm.com> Mon Aug 23 16:40:57 2021 +0100
committer Kevin Cheng <kevin.cheng@arm.com> Mon Aug 23 12:58:31 2021 -0700
tree e9afd7343c0fd03e54323fba4ae406e95d69248d
parent 3ce563449c1e607b016b82c5dbb6e33883f846a5

Rename DIV operator to INTDIV

 * In line with the TOSA spec the DIV operator has been renamed INTDIV

Signed-off-by: Matthew Haddon <matthew.haddon@arm.com>
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: I17407dd50985d117e2e565ffb45afb3424e5a139

include/operator.def

diff --git a/include/operator.def b/include/operator.def
index 0329dd2..83155d8 100644
--- a/include/operator.def
+++ b/include/operator.def
@@ -49,7 +49,7 @@
 DEF_OPERATOR(bitwise_and,             BITWISE_AND,              BitwiseAnd,             None,             None)
 DEF_OPERATOR(bitwise_or,              BITWISE_OR,               BitwiseOr,              None,             None)
 DEF_OPERATOR(bitwise_xor,             BITWISE_XOR,              BitwiseXor,             None,             None)
-DEF_OPERATOR(div,                     DIV,                      Div,                    None,             None)
+DEF_OPERATOR(intdiv,                  INTDIV,                   Intdiv,                 None,             None)
 DEF_OPERATOR(logical_and,             LOGICAL_AND,              LogicalAnd,             None,             None)
 DEF_OPERATOR(logical_left_shift,      LOGICAL_LEFT_SHIFT,       LogicalLeftShift,       None,             None)
 DEF_OPERATOR(logical_right_shift,     LOGICAL_RIGHT_SHIFT,      LogicalRightShift,      None,             None)

include/tosa_generated.h

diff --git a/include/tosa_generated.h b/include/tosa_generated.h
index 0f73819..af8b5bb 100644
--- a/include/tosa_generated.h
+++ b/include/tosa_generated.h
@@ -199,7 +199,7 @@
   Op_BITWISE_AND = 16,
   Op_BITWISE_OR = 17,
   Op_BITWISE_XOR = 18,
-  Op_DIV = 19,
+  Op_INTDIV = 19,
   Op_LOGICAL_AND = 20,
   Op_LOGICAL_LEFT_SHIFT = 21,
   Op_LOGICAL_RIGHT_SHIFT = 22,
@@ -274,7 +274,7 @@
     Op_BITWISE_AND,
     Op_BITWISE_OR,
     Op_BITWISE_XOR,
-    Op_DIV,
+    Op_INTDIV,
     Op_LOGICAL_AND,
     Op_LOGICAL_LEFT_SHIFT,
     Op_LOGICAL_RIGHT_SHIFT,
@@ -349,7 +349,7 @@
     "BITWISE_AND",
     "BITWISE_OR",
     "BITWISE_XOR",
-    "DIV",
+    "INTDIV",
     "LOGICAL_AND",
     "LOGICAL_LEFT_SHIFT",
     "LOGICAL_RIGHT_SHIFT",

python/tosa/Op.py

diff --git a/python/tosa/Op.py b/python/tosa/Op.py
index 0a4cdda..0c29224 100644
--- a/python/tosa/Op.py
+++ b/python/tosa/Op.py
@@ -37,7 +37,7 @@
     BITWISE_AND = 16
     BITWISE_OR = 17
     BITWISE_XOR = 18
-    DIV = 19
+    INTDIV = 19
     LOGICAL_AND = 20
     LOGICAL_LEFT_SHIFT = 21
     LOGICAL_RIGHT_SHIFT = 22

schema/tosa.fbs

diff --git a/schema/tosa.fbs b/schema/tosa.fbs
index 9c8add8..daf6475 100644
--- a/schema/tosa.fbs
+++ b/schema/tosa.fbs
@@ -64,7 +64,7 @@
   BITWISE_AND,
   BITWISE_OR,
   BITWISE_XOR,
-  DIV,
+  INTDIV,
   LOGICAL_AND,
   LOGICAL_LEFT_SHIFT,
   LOGICAL_RIGHT_SHIFT,