Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "src/cpu/kernels/CpuDirectConv3dKernel.h" |
| 25 | |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 26 | #include "arm_compute/core/Error.h" |
| 27 | #include "arm_compute/core/Helpers.h" |
| 28 | #include "arm_compute/core/IAccessWindow.h" |
| 29 | #include "arm_compute/core/ITensor.h" |
| 30 | #include "arm_compute/core/Types.h" |
| 31 | #include "arm_compute/core/Utils.h" |
| 32 | #include "arm_compute/core/Validate.h" |
| 33 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
| 34 | #include "src/core/CPP/Validate.h" |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 35 | #include "src/core/NEON/wrapper/wrapper.h" |
| 36 | #include "src/core/common/Registrars.h" |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 37 | #include "src/core/helpers/AutoConfiguration.h" |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 38 | #include "src/cpu/kernels/conv3d/neon/list.h" |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 39 | |
| 40 | #include <algorithm> |
| 41 | |
| 42 | using namespace arm_compute::detail; |
| 43 | |
| 44 | namespace arm_compute |
| 45 | { |
| 46 | namespace cpu |
| 47 | { |
| 48 | namespace kernels |
| 49 | { |
| 50 | namespace |
| 51 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 52 | struct DirectConv3dSelectorData |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 53 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 54 | DataType dt; |
| 55 | const CPUInfo &ci; |
| 56 | }; |
| 57 | using DirectConv3dSelectorPtr = std::add_pointer<bool(const DirectConv3dSelectorData &data)>::type; |
| 58 | using DirectConv3dKernelPtr = std::add_pointer<void(const ITensor *, const ITensor *, const ITensor *, ITensor *, const Conv3dInfo &, const Window &)>::type; |
| 59 | struct DirectConv3dKernel |
| 60 | { |
| 61 | const char *name; |
| 62 | const DirectConv3dSelectorPtr is_selected; |
| 63 | DirectConv3dKernelPtr ukernel; |
| 64 | }; |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 65 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 66 | static const DirectConv3dKernel available_kernels[] = |
| 67 | { |
| 68 | #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) |
| 69 | { |
| 70 | "neon_fp16_directconv3d", |
| 71 | [](const DirectConv3dSelectorData & data) { return data.dt == DataType::F16 && data.ci.has_fp16(); }, |
| 72 | REGISTER_FP16_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float16_t>) |
| 73 | }, |
| 74 | #endif /* !defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */ |
| 75 | { |
| 76 | "neon_fp32_directconv3d", |
| 77 | [](const DirectConv3dSelectorData & data) { return data.dt == DataType::F32; }, |
| 78 | REGISTER_FP32_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float>) |
| 79 | } |
| 80 | }; |
| 81 | |
| 82 | /** Micro-kernel selector |
| 83 | * |
| 84 | * @param[in] data Selection data passed to help pick the appropriate micro-kernel |
| 85 | * |
| 86 | * @return A matching micro-kernel else nullptr |
| 87 | */ |
| 88 | const DirectConv3dKernel *get_implementation(const DirectConv3dSelectorData &data) |
| 89 | { |
| 90 | for(const auto &uk : available_kernels) |
| 91 | { |
| 92 | if(uk.is_selected(data)) |
| 93 | { |
| 94 | return &uk; |
| 95 | } |
| 96 | } |
| 97 | return nullptr; |
| 98 | } |
| 99 | |
| 100 | Status validate_arguments(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info) |
| 101 | { |
| 102 | const auto *uk = get_implementation(DirectConv3dSelectorData{ src0->data_type(), CPUInfo::get() }); |
| 103 | ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr); |
| 104 | |
| 105 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst); |
| 106 | ARM_COMPUTE_RETURN_ERROR_ON(src0->data_layout() != DataLayout::NDHWC); |
| 107 | ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src0); |
| 108 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src0, 1, DataType::F16, DataType::F32); |
| 109 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src0, src1); |
| 110 | |
| 111 | const DataLayout data_layout = src0->data_layout(); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 112 | const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL); |
| 113 | |
| 114 | // Weight layout is D, H, W, Cin, Cout |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 115 | ARM_COMPUTE_RETURN_ERROR_ON(src1->num_dimensions() > 5); |
| 116 | ARM_COMPUTE_RETURN_ERROR_ON(src1->dimension(1) != src0->dimension(channel_idx)); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 117 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 118 | if(src2 != nullptr) |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 119 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 120 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src1, src2); |
| 121 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->dimension(0) != src1->dimension(0), |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 122 | "biases size and number of output feature maps should match"); |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 123 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->num_dimensions() > 1, "biases should be one dimensional"); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | // Checks performed when output is configured |
| 127 | if(dst->total_size() != 0) |
| 128 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 129 | TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 130 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 131 | DataType data_type = src0->data_type(); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 132 | |
| 133 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(dst->tensor_shape(), output_shape); |
| 134 | ARM_COMPUTE_RETURN_ERROR_ON(dst->data_type() != data_type); |
| 135 | } |
| 136 | |
| 137 | return Status{}; |
| 138 | } |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 139 | } |
| 140 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 141 | void CpuDirectConv3dKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv_info) |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 142 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 143 | ARM_COMPUTE_UNUSED(src2); |
| 144 | ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 145 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 146 | const auto *uk = get_implementation(DirectConv3dSelectorData{ src0->data_type(), CPUInfo::get() }); |
| 147 | ARM_COMPUTE_ERROR_ON_NULLPTR(uk); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 148 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 149 | _conv_info = conv_info; |
| 150 | _run_method = uk->ukernel; |
| 151 | _name = std::string("CpuDirectConv3dKernel").append("/").append(uk->name); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 152 | |
| 153 | // Get convolved dimensions |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 154 | TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 155 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 156 | DataType data_type = src0->data_type(); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 157 | |
| 158 | // Output auto inizialitation if not yet initialized |
| 159 | auto_init_if_empty(*dst, output_shape, 1, data_type); |
| 160 | |
| 161 | // Perform validation step |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 162 | ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src0, src1, src2, dst, conv_info)); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 163 | |
| 164 | // Configure kernel window |
| 165 | Window win = calculate_max_window(*dst, Steps()); |
| 166 | ICpuKernel::configure(win); |
| 167 | } |
| 168 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 169 | Status CpuDirectConv3dKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info) |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 170 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 171 | ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src0, src1, src2, dst, conv_info)); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 172 | |
| 173 | return Status{}; |
| 174 | } |
| 175 | |
| 176 | void CpuDirectConv3dKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) |
| 177 | { |
| 178 | ARM_COMPUTE_UNUSED(info); |
| 179 | ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this); |
| 180 | ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window); |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 181 | ARM_COMPUTE_ERROR_ON(_run_method == nullptr); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 182 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 183 | auto src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0); |
| 184 | auto src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1); |
| 185 | auto src2 = tensors.get_const_tensor(TensorType::ACL_SRC_2); |
| 186 | auto dst = tensors.get_tensor(TensorType::ACL_DST); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 187 | |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 188 | _run_method(src0, src1, src2, dst, _conv_info, window); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | const char *CpuDirectConv3dKernel::name() const |
| 192 | { |
Sheri Zhang | 5dda217 | 2021-10-15 19:54:17 +0100 | [diff] [blame^] | 193 | return _name.c_str(); |
Sheri Zhang | 6d9c982 | 2021-09-24 16:02:57 +0100 | [diff] [blame] | 194 | } |
| 195 | } // namespace kernels |
| 196 | } // namespace cpu |
| 197 | } // namespace arm_compute |