Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 1 | /* |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 2 | * Copyright (c) 2021-2022 Arm Limited. |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 24 | #include "src/cpu/kernels/CpuSubKernel.h" |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 25 | |
| 26 | #include "arm_compute/core/TensorInfo.h" |
| 27 | #include "arm_compute/core/Validate.h" |
| 28 | #include "src/core/CPP/Validate.h" |
| 29 | #include "src/core/common/Registrars.h" |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 30 | #include "src/core/helpers/AutoConfiguration.h" |
| 31 | #include "src/core/helpers/WindowHelpers.h" |
Georgios Pinitas | 7891a73 | 2021-08-20 21:39:25 +0100 | [diff] [blame] | 32 | #include "src/cpu/kernels/sub/neon/list.h" |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 33 | |
Fadi Arafeh | 73bb6b7 | 2022-10-06 16:20:14 +0000 | [diff] [blame^] | 34 | namespace |
| 35 | { |
| 36 | static constexpr size_t default_mws_N1_fp32_neon = 24385; |
| 37 | static constexpr size_t default_mws_V1_fp32_neon = 40520; |
| 38 | } |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 39 | namespace arm_compute |
| 40 | { |
| 41 | namespace cpu |
| 42 | { |
| 43 | namespace kernels |
| 44 | { |
| 45 | namespace |
| 46 | { |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 47 | static const std::vector<CpuSubKernel::SubKernel> available_kernels = |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 48 | { |
| 49 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 50 | "neon_fp32_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 51 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::F32); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 52 | REGISTER_FP32_NEON(arm_compute::cpu::sub_same_neon<float>) |
| 53 | }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 54 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 55 | "neon_fp16_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 56 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::F16) && data.isa.fp16; }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 57 | REGISTER_FP16_NEON(arm_compute::cpu::sub_same_neon<float16_t>) |
| 58 | }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 59 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 60 | "neon_u8_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 61 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::U8); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 62 | REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<uint8_t>) |
| 63 | }, |
| 64 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 65 | "neon_s16_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 66 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::S16); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 67 | REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int16_t>) |
| 68 | }, |
| 69 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 70 | "neon_s32_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 71 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::S32); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 72 | REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int32_t>) |
| 73 | }, |
| 74 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 75 | "neon_qu8_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 76 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 77 | REGISTER_QASYMM8_NEON(arm_compute::cpu::sub_qasymm8_neon) |
| 78 | }, |
| 79 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 80 | "neon_qs8_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 81 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8_SIGNED); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 82 | REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::sub_qasymm8_signed_neon) |
| 83 | }, |
| 84 | { |
Georgios Pinitas | da81675 | 2021-07-02 09:22:14 +0100 | [diff] [blame] | 85 | "neon_qs16_sub", |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 86 | [](const DataTypeISASelectorData & data) { return (data.dt == DataType::QSYMM16); }, |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 87 | REGISTER_QSYMM16_NEON(arm_compute::cpu::sub_qsymm16_neon) |
| 88 | }, |
| 89 | }; |
| 90 | |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 91 | inline Status validate_arguments(const ITensorInfo &src0, const ITensorInfo &src1, const ITensorInfo &dst, ConvertPolicy policy) |
| 92 | { |
| 93 | ARM_COMPUTE_UNUSED(policy); |
| 94 | ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(&src0); |
| 95 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&src0, 1, DataType::U8, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM16, DataType::S16, DataType::S32, DataType::F16, |
| 96 | DataType::F32); |
Georgios Pinitas | da81675 | 2021-07-02 09:22:14 +0100 | [diff] [blame] | 97 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(&src0, &src1); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 98 | |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 99 | const auto *uk = CpuSubKernel::get_implementation(DataTypeISASelectorData{ src0.data_type(), CPUInfo::get().get_isa() }); |
| 100 | |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 101 | ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr); |
| 102 | |
| 103 | const TensorShape out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape()); |
| 104 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(out_shape.total_size() == 0, "Inputs are not broadcast compatible"); |
| 105 | |
Georgios Pinitas | da81675 | 2021-07-02 09:22:14 +0100 | [diff] [blame] | 106 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(is_data_type_quantized(src0.data_type()) && (policy == ConvertPolicy::WRAP), |
| 107 | "Convert policy cannot be WRAP if datatype is quantized"); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 108 | |
| 109 | // Validate in case of configured dst |
| 110 | if(dst.total_size() > 0) |
| 111 | { |
Georgios Pinitas | da81675 | 2021-07-02 09:22:14 +0100 | [diff] [blame] | 112 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(&src0, &dst); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 113 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(detail::have_different_dimensions(out_shape, dst.tensor_shape(), 0), |
| 114 | "Wrong shape for dst"); |
| 115 | } |
| 116 | return Status{}; |
| 117 | } |
| 118 | } // namespace |
| 119 | |
| 120 | void CpuSubKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy) |
| 121 | { |
| 122 | ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst); |
| 123 | ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(*src0, *src1, *dst, policy)); |
| 124 | |
SiCongLi | c7b1e84 | 2021-02-22 14:28:33 +0000 | [diff] [blame] | 125 | const TensorShape &out_shape = TensorShape::broadcast_shape(src0->tensor_shape(), src1->tensor_shape()); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 126 | |
| 127 | // Auto initialize dst if not initialized |
| 128 | set_shape_if_empty(*dst, out_shape); |
Georgios Pinitas | da81675 | 2021-07-02 09:22:14 +0100 | [diff] [blame] | 129 | set_data_type_if_unknown(*dst, src0->data_type()); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 130 | |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 131 | const auto *uk = CpuSubKernel::get_implementation(DataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa() }); |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 132 | ARM_COMPUTE_ERROR_ON_NULLPTR(uk); |
| 133 | |
| 134 | _policy = policy; |
| 135 | _run_method = uk->ukernel; |
| 136 | _name = std::string("CpuSubKernel").append("/").append(uk->name); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 137 | |
| 138 | // CpuSubKernel doesn't need padding so update_window_and_padding() can be skipped |
Jakub Sujak | 842ad21 | 2022-09-17 13:08:56 +0100 | [diff] [blame] | 139 | Window win; |
| 140 | std::tie(win, _split_dimension) = calculate_squashed_or_max_window(*src0, *src1); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 141 | |
| 142 | ICpuKernel::configure(win); |
| 143 | } |
| 144 | |
Fadi Arafeh | 73bb6b7 | 2022-10-06 16:20:14 +0000 | [diff] [blame^] | 145 | size_t CpuSubKernel::get_mws(const CPUInfo &platform, size_t thread_count) const |
| 146 | { |
| 147 | ARM_COMPUTE_UNUSED(thread_count); |
| 148 | |
| 149 | #if defined(ENABLE_FP32_KERNELS) |
| 150 | if(this->_run_method == &sub_same_neon<float>) |
| 151 | { |
| 152 | size_t mws = ICPPKernel::default_mws; |
| 153 | if(platform.get_cpu_model() == CPUModel::N1) |
| 154 | { |
| 155 | mws = default_mws_N1_fp32_neon; |
| 156 | } |
| 157 | else if(platform.get_cpu_model() == CPUModel::V1) |
| 158 | { |
| 159 | mws = default_mws_V1_fp32_neon; |
| 160 | } |
| 161 | else |
| 162 | { |
| 163 | return ICPPKernel::default_mws; |
| 164 | } |
| 165 | |
| 166 | // tensor is 1D or was re-interpreted as 1D |
| 167 | if(this->window().shape().num_dimensions() == 1) |
| 168 | { |
| 169 | return mws; |
| 170 | } |
| 171 | else |
| 172 | { |
| 173 | // scale mws down by the number of elements along all the dimensions (x, z, w, etc) except the one |
| 174 | // that we parallelize along (the y dimension). This allows for parallelization when the Y_SIZE is small |
| 175 | // but the other sizes are large, which boosts performance. |
| 176 | mws = static_cast<size_t>(mws / (this->window().num_iterations_total() / this->window().num_iterations(1))); |
| 177 | return std::max(static_cast<size_t>(1), mws); |
| 178 | } |
| 179 | } |
| 180 | #else /* ENABLE_FP32_KERNELS */ |
| 181 | ARM_COMPUTE_UNUSED(platform); |
| 182 | #endif /* ENABLE_FP32_KERNELS */ |
| 183 | return ICPPKernel::default_mws; |
| 184 | } |
| 185 | |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 186 | Status CpuSubKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy) |
| 187 | { |
| 188 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst); |
| 189 | ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(*src0, *src1, *dst, policy)); |
| 190 | |
| 191 | return Status{}; |
| 192 | } |
| 193 | |
| 194 | void CpuSubKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) |
| 195 | { |
| 196 | ARM_COMPUTE_UNUSED(info); |
| 197 | ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this); |
| 198 | ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window); |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 199 | ARM_COMPUTE_ERROR_ON(_run_method == nullptr); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 200 | |
| 201 | const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0); |
| 202 | const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1); |
| 203 | ITensor *dst = tensors.get_tensor(TensorType::ACL_DST); |
| 204 | |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 205 | _run_method(src0, src1, dst, _policy, window); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | const char *CpuSubKernel::name() const |
| 209 | { |
Georgios Pinitas | 5fdde99 | 2021-06-25 05:42:57 +0100 | [diff] [blame] | 210 | return _name.c_str(); |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 211 | } |
Giorgio Arena | 5ae8d80 | 2021-11-18 18:02:13 +0000 | [diff] [blame] | 212 | |
| 213 | const std::vector<CpuSubKernel::SubKernel> &CpuSubKernel::get_available_kernels() |
| 214 | { |
| 215 | return available_kernels; |
| 216 | } |
| 217 | |
Sheri Zhang | fc6744a | 2021-01-13 15:54:05 +0000 | [diff] [blame] | 218 | } // namespace kernels |
| 219 | } // namespace cpu |
| 220 | } // namespace arm_compute |