blob: 7be2d6d230ec2c87bfadd1573bfd3aed35497779 [file] [log] [blame]
Michalis Spyrou96f977e2021-07-01 12:20:56 +01001/*
ramelg01a1f78512022-06-29 16:28:10 +01002 * Copyright (c) 2021-2022 Arm Limited.
Michalis Spyrou96f977e2021-07-01 12:20:56 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
Georgios Pinitas7891a732021-08-20 21:39:25 +010024#include "src/cpu/operators/CpuWinogradConv2d.h"
Michalis Spyrou96f977e2021-07-01 12:20:56 +010025#include "arm_compute/core/Error.h"
26#include "arm_compute/core/Utils.h"
27#include "arm_compute/core/Validate.h"
28#include "arm_compute/core/utils/misc/ShapeCalculator.h"
29#include "arm_compute/core/utils/quantization/AsymmHelpers.h"
30#include "arm_compute/runtime/FunctionDescriptors.h"
31#include "arm_compute/runtime/NEON/NEScheduler.h"
ramelg013ae3d882021-09-12 23:07:47 +010032#include "src/common/utils/Log.h"
Michalis Spyrou96f977e2021-07-01 12:20:56 +010033#include "src/core/CPP/Validate.h"
ramelg01a1f78512022-06-29 16:28:10 +010034#include "src/core/NEON/kernels/assembly/winograd.hpp"
35#include "src/core/NEON/kernels/convolution/common/tensor.hpp"
Michalis Spyrou96f977e2021-07-01 12:20:56 +010036#include "src/core/NEON/kernels/convolution/common/utils.hpp"
Michalis Spyrou96f977e2021-07-01 12:20:56 +010037#include "src/core/helpers/MemoryHelpers.h"
ramelg01a1f78512022-06-29 16:28:10 +010038#include "src/core/helpers/WindowHelpers.h"
39#include "src/core/utils/AssemblyUtils.h"
Georgios Pinitas7891a732021-08-20 21:39:25 +010040#include "src/cpu/kernels/CpuWinogradConv2dKernel.h"
ramelg01a1f78512022-06-29 16:28:10 +010041#include "src/cpu/kernels/assembly/arm_gemm.hpp"
Georgios Pinitas7891a732021-08-20 21:39:25 +010042#include "src/cpu/operators/CpuActivation.h"
43#include "src/cpu/operators/CpuPermute.h"
Georgios Pinitas7891a732021-08-20 21:39:25 +010044#include "src/cpu/utils/CpuAuxTensorHandler.h"
Michalis Spyrou96f977e2021-07-01 12:20:56 +010045#include "support/Cast.h"
46
Michalis Spyrou96f977e2021-07-01 12:20:56 +010047namespace arm_compute
48{
49namespace cpu
50{
51using namespace arm_compute::experimental;
52using namespace arm_compute::utils::cast;
53
54namespace
55{
ramelg01a1f78512022-06-29 16:28:10 +010056inline Tensor4DShape internal_get_shape(const ITensorInfo *in)
Michalis Spyrou96f977e2021-07-01 12:20:56 +010057{
ramelg01a1f78512022-06-29 16:28:10 +010058 const DataLayout data_layout = in->data_layout();
59 const int in_width = in->dimension(get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH));
60 const int in_height = in->dimension(get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT));
61 const int in_channels = in->dimension(get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL));
62 const int in_batches = in->dimension(get_data_layout_dimension_index(data_layout, DataLayoutDimension::BATCHES));
Michalis Spyrou96f977e2021-07-01 12:20:56 +010063
64 return Tensor4DShape{ in_batches, in_height, in_width, in_channels };
65}
66
Michele Di Giorgiod9cdf142021-07-02 15:17:08 +010067Status validate_arguments(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const PadStrideInfo &conv_info)
Michalis Spyrou96f977e2021-07-01 12:20:56 +010068{
ramelg01a1f78512022-06-29 16:28:10 +010069 ARM_COMPUTE_UNUSED(dst, weights);
Michele Di Giorgiod9cdf142021-07-02 15:17:08 +010070 ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src);
Michalis Spyrou96f977e2021-07-01 12:20:56 +010071
72 ARM_COMPUTE_RETURN_ERROR_ON_MSG(conv_info.stride().first != 1 || conv_info.stride().second != 1, "Winograd layer only supports unit strides.");
73 if(biases != nullptr)
74 {
Michele Di Giorgiod9cdf142021-07-02 15:17:08 +010075 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, biases);
Michalis Spyrou96f977e2021-07-01 12:20:56 +010076 ARM_COMPUTE_RETURN_ERROR_ON(biases->num_dimensions() > 1);
77 }
ramelg01a1f78512022-06-29 16:28:10 +010078 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src, 1, DataType::F16, DataType::F32);
79 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, weights);
80 return Status{};
Michalis Spyrou96f977e2021-07-01 12:20:56 +010081}
ramelg01a1f78512022-06-29 16:28:10 +010082
83bool get_winograd_kernel_implementation(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *dst,
84 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, bool enable_fast_math,
85 arm_conv::winograd::WinogradImpl *winograd_impl, std::unique_ptr<arm_conv::ConvolutionArgs> &conv_args)
Michalis Spyrou96f977e2021-07-01 12:20:56 +010086{
ramelg01a1f78512022-06-29 16:28:10 +010087 arm_conv::winograd::WinogradConfig winograd_cfg;
88 arm_gemm::GemmConfig cfg;
89
90 const DataType data_type = src->data_type();
91 Tensor4DShape in_shape{ internal_get_shape(src) };
92 Tensor4DShape out_shape{ internal_get_shape(dst) };
93 Tensor4DShape kernel_shape{ internal_get_shape(weights) };
94 uint32_t nthreads = NEScheduler::get().num_threads();
95 // Get configuration arguments for Winograd
96 winograd_cfg.output_rows = 0;
97 winograd_cfg.output_cols = 0;
98 conv_args = std::make_unique<arm_conv::ConvolutionArgs>(
99 in_shape.n_batches,
100 arm_conv::Shape2D{ static_cast<uint32_t>(in_shape.n_rows), static_cast<uint32_t>(in_shape.n_cols) },
101 in_shape.n_channels,
102 conv_info.pad_top(),
103 conv_info.pad_left(),
104 arm_conv::Shape2D{ static_cast<uint32_t>(out_shape.n_rows), static_cast<uint32_t>(out_shape.n_cols) },
105 out_shape.n_channels,
106 arm_conv::Shape2D{ static_cast<uint32_t>(kernel_shape.n_rows), static_cast<uint32_t>(kernel_shape.n_cols) },
107 assembly_utils::map_to_arm_gemm_activation(act_info));
108
109 bool success = false;
110 if(data_type == DataType::F32)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100111 {
ramelg01a1f78512022-06-29 16:28:10 +0100112 success = arm_conv::winograd::get_implementation<float>(
113 *winograd_impl, &CPUInfo::get(), *conv_args, nthreads, enable_fast_math, &winograd_cfg, nullptr);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100114 }
ramelg01a1f78512022-06-29 16:28:10 +0100115#if defined(__aarch64__) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
116 else if(data_type == DataType::F16)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100117 {
ramelg01a1f78512022-06-29 16:28:10 +0100118 success = arm_conv::winograd::get_implementation<__fp16>(
119 *winograd_impl, &CPUInfo::get(), *conv_args, nthreads, enable_fast_math, &winograd_cfg, nullptr);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100120 }
ramelg01a1f78512022-06-29 16:28:10 +0100121#endif // defined(__aarch64__) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
122 else
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100123 {
ramelg01a1f78512022-06-29 16:28:10 +0100124 success = false;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100125 }
ramelg01a1f78512022-06-29 16:28:10 +0100126 return success;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100127}
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100128inline bool fuse_function_supported(const ActivationLayerInfo &act_info)
129{
130 return act_info.activation() == ActivationLayerInfo::ActivationFunction::RELU || act_info.activation() == ActivationLayerInfo::ActivationFunction::BOUNDED_RELU;
131}
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100132} // namespace
133
134CpuWinogradConv2d::CpuWinogradConv2d()
ramelg01a1f78512022-06-29 16:28:10 +0100135
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100136 : _gemm_function(std::make_unique<CpuGemm>()),
137 _activation_func(std::make_unique<CpuActivation>()),
ramelg01a1f78512022-06-29 16:28:10 +0100138 _transform_input_kernel(nullptr),
139 _transform_output_kernel(nullptr),
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100140 _permute_input(std::make_unique<CpuPermute>()),
141 _permute_output(std::make_unique<CpuPermute>()),
142 _permute_weights(std::make_unique<CpuPermute>()),
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100143 _aux_mem(AuxTensorIdx::Count),
ramelg01a1f78512022-06-29 16:28:10 +0100144 _conv_args{ nullptr },
145 _winograd_impl{},
146 _data_layout(),
147 _winograd_transformed_input{},
148 _winograd_transformed_output{},
149 _winograd_transformed_weights{},
150 _input_workspace(),
151 _output_workspace(),
152 _weights_hwio(),
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100153 _input_nhwc(),
154 _output_nhwc(),
ramelg01a1f78512022-06-29 16:28:10 +0100155 _is_prepared{ false },
156 _run_activation{ false }
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100157{
158}
159
160CpuWinogradConv2d::~CpuWinogradConv2d() = default;
161
162void CpuWinogradConv2d::configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst,
163 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, bool enable_fast_math)
164{
165 ARM_COMPUTE_ERROR_ON_NULLPTR(src, weights, dst);
166 ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src, weights, biases, dst, conv_info));
ramelg013ae3d882021-09-12 23:07:47 +0100167 ARM_COMPUTE_LOG_PARAMS(src, weights, biases, dst, conv_info, act_info, enable_fast_math);
ramelg01a1f78512022-06-29 16:28:10 +0100168 ARM_COMPUTE_UNUSED(biases);
169 const DataType data_type = src->data_type();
170 uint32_t nthreads = NEScheduler::get().num_threads();
171 _data_layout = src->data_layout();
172 const Tensor4DShape kernel_shape{ internal_get_shape(weights) };
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100173
ramelg01a1f78512022-06-29 16:28:10 +0100174 bool success = get_winograd_kernel_implementation(src, weights, dst, conv_info, act_info, enable_fast_math, &_winograd_impl, _conv_args);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100175
ramelg01a1f78512022-06-29 16:28:10 +0100176 ARM_COMPUTE_EXIT_ON_MSG_VAR(!success, "Unsupported kernel size: %d x %d.\n", kernel_shape.n_rows, kernel_shape.n_cols);
177 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using input transform: %s\n", _winograd_impl.input_transform->get_name().c_str());
178 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using weight transform: %s\n", _winograd_impl.input_transform->get_name().c_str());
179 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using output transform: %s\n", _winograd_impl.input_transform->get_name().c_str());
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100180
ramelg01a1f78512022-06-29 16:28:10 +0100181 const bool has_impl = ((_winograd_impl.input_transform != nullptr) && (_winograd_impl.output_transform != nullptr) && (_winograd_impl.gemm_args != nullptr));
182 if(has_impl)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100183 {
ramelg01a1f78512022-06-29 16:28:10 +0100184 // Determine how much working space is required, allocate it.
185 const size_t input_workspace_size = _winograd_impl.input_transform->get_working_space_size(*_conv_args, nthreads);
186 const size_t output_workspace_size = _winograd_impl.output_transform->get_working_space_size(*_conv_args, nthreads);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100187
ramelg01a1f78512022-06-29 16:28:10 +0100188 TensorInfo input_workspace_info(TensorShape(input_workspace_size), 1, DataType::U8);
189 TensorInfo output_workspace_info(TensorShape(output_workspace_size), 1, DataType::U8);
190 _input_workspace = input_workspace_info;
191 _output_workspace = output_workspace_info;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100192
ramelg01a1f78512022-06-29 16:28:10 +0100193 const auto &wds = _winograd_impl.winograd_spec;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100194
ramelg01a1f78512022-06-29 16:28:10 +0100195 // Preparing winograd transformed input tensor
196 const size_t data_type_size = src->element_size();
197 const uint32_t m = _winograd_impl.gemm_args->_Msize; // Total number of tiles
198 const uint32_t k = _winograd_impl.gemm_args->_Ksize; // Input channels
199 const uint32_t n = _winograd_impl.gemm_args->_Nsize; // Output channels
200 const uint32_t n_gemms = _winograd_impl.gemm_args->_nmulti;
201 const uint32_t n_batches = _winograd_impl.gemm_args->_nbatches;
202 constexpr size_t storage_alignment = 64;
203
204 const TensorShape a_shape(k, m, n_batches, n_gemms);
205 Strides a_strides(data_type_size);
206 a_strides.set(1, data_type_size * _winograd_impl.winograd_spec.input_ld_row);
207 a_strides.set(2, data_type_size * _winograd_impl.winograd_spec.input_ld_batch);
208 a_strides.set(3, data_type_size * _winograd_impl.winograd_spec.input_ld_matrix);
209
210 const TensorShape b_shape(n, k, n_gemms);
211 Strides b_strides(data_type_size);
212 b_strides.set(1, data_type_size * _winograd_impl.winograd_spec.weight_ld_row);
213 b_strides.set(2, data_type_size * _winograd_impl.winograd_spec.weight_ld_matrix);
214
215 const TensorShape d_shape(n, m, n_batches, n_gemms);
216 Strides d_strides(data_type_size);
217 d_strides.set(1, data_type_size * _winograd_impl.winograd_spec.output_ld_row);
218 d_strides.set(2, data_type_size * _winograd_impl.winograd_spec.output_ld_batch);
219 d_strides.set(3, data_type_size * _winograd_impl.winograd_spec.output_ld_matrix);
220
221 TensorInfo a_info{};
222 TensorInfo b_info{};
223 TensorInfo d_info{};
224 a_info.init(a_shape, 1, data_type, a_strides, 0, wds.input_matrix_size_bytes);
225 b_info.init(b_shape, 1, data_type, b_strides, 0, wds.weight_matrix_size_bytes);
226 d_info.init(d_shape, 1, data_type, d_strides, 0, wds.output_matrix_size_bytes);
227
228 _winograd_transformed_input = a_info;
229 _winograd_transformed_weights = b_info;
230 _winograd_transformed_output = d_info;
231
232 PermutationVector weights_permutation_vector(3U, 0U, 1U, 2U);
233
234 // Configure the kernel to transform the input tensor from NCHW -> NHWC
235 if(_data_layout == DataLayout::NCHW)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100236 {
ramelg01a1f78512022-06-29 16:28:10 +0100237 _permute_input->configure(src, &_input_nhwc, PermutationVector(2U, 0U, 1U));
238 weights_permutation_vector = PermutationVector(3U, 2U, 0U, 1U);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100239 }
ramelg01a1f78512022-06-29 16:28:10 +0100240
241 // Re-order a weight tensor from [Output feature map x Input feature map x Height x Width] to [Height x Width x Input feature map x Output feature map]
242 _permute_weights->configure(weights, &_weights_hwio, weights_permutation_vector);
243
244 // Reorder the convoluted output to ACL's ordering NCHW
245 if(_data_layout == DataLayout::NCHW)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100246 {
ramelg01a1f78512022-06-29 16:28:10 +0100247 // configure and allocate dst tensor to be used to convert from winograd domain to spatial domain when calling to reshape_output()
248 TensorInfo info(TensorShape(dst->dimension(2), dst->dimension(0),
249 dst->dimension(1), dst->dimension(3)),
250 1, dst->data_type());
251 _output_nhwc = info;
252 _permute_output->configure(&_output_nhwc, dst, PermutationVector(1U, 2U, 0U));
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100253 }
ramelg01a1f78512022-06-29 16:28:10 +0100254
255 // Configure GEMM function
256 _gemm_function->configure(&_winograd_transformed_input, &_winograd_transformed_weights, nullptr, &_winograd_transformed_output, 1.0f, 0.f);
257
258 //Configure Activation Layer
259 _run_activation = act_info.enabled() && !fuse_function_supported(act_info);
260 if(_run_activation)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100261 {
ramelg01a1f78512022-06-29 16:28:10 +0100262 _activation_func->configure(dst, nullptr, act_info);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100263 }
ramelg01a1f78512022-06-29 16:28:10 +0100264
265 auto asm_mem_req = _gemm_function->workspace();
266 _aux_mem[GemmWorkspace] = asm_mem_req[GemmWorkspace];
267 _aux_mem[Pretranspose] = asm_mem_req[Pretranspose];
268 _aux_mem[InterleavedLHS] = asm_mem_req[InterleavedLHS];
269 _aux_mem[TransposedRHS] = asm_mem_req[TransposedRHS];
270 _aux_mem[TempResult] = asm_mem_req[TempResult];
271
272 // Request temporary memory. Overlap memory needed for Input/Output transformations as they run on different non-overlapping time-steps.
273 _aux_mem[TransformedInput] = MemoryInfo(offset_int_vec(TransformedInput), MemoryLifetime::Temporary, wds.input_matrix_size_bytes, storage_alignment);
274 _aux_mem[TransformedOutput] = MemoryInfo(offset_int_vec(TransformedOutput), MemoryLifetime::Temporary, wds.output_matrix_size_bytes, storage_alignment);
275 _aux_mem[WorkspaceIO] = MemoryInfo(offset_int_vec(WorkspaceIO), MemoryLifetime::Temporary, std::max(input_workspace_size, output_workspace_size));
276 _aux_mem[PermutedWeights] = MemoryInfo(offset_int_vec(PermutedWeights), MemoryLifetime::Prepare, _weights_hwio.total_size());
277 _aux_mem[TransformedWeights] = MemoryInfo(offset_int_vec(TransformedWeights), MemoryLifetime::Persistent, wds.weight_matrix_size_bytes, storage_alignment);
278 if(_data_layout == DataLayout::NCHW)
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100279 {
ramelg01a1f78512022-06-29 16:28:10 +0100280 _aux_mem[PermutedInput].merge(offset_int_vec(PermutedInput), src->total_size());
281 _aux_mem[PermutedOutput].merge(offset_int_vec(PermutedOutput), dst->total_size());
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100282 }
Georgios Pinitas87a74ef2021-08-20 17:26:45 +0100283 }
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100284}
Michele Di Giorgiod9cdf142021-07-02 15:17:08 +0100285Status CpuWinogradConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst,
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100286 const PadStrideInfo &conv_info, const ActivationLayerInfo &act_info, bool enable_fast_math)
287{
Michele Di Giorgiod9cdf142021-07-02 15:17:08 +0100288 ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, weights, dst);
289 ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src, weights, biases, dst, conv_info));
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100290
ramelg01a1f78512022-06-29 16:28:10 +0100291 const Tensor4DShape kernel_shape{ internal_get_shape(weights) };
292 arm_conv::winograd::WinogradImpl winograd_impl{};
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100293
ramelg01a1f78512022-06-29 16:28:10 +0100294 std::unique_ptr<arm_conv::ConvolutionArgs> conv_args;
295 const bool success = get_winograd_kernel_implementation(src, weights, dst, conv_info, act_info, enable_fast_math, &winograd_impl, conv_args);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100296
ramelg01a1f78512022-06-29 16:28:10 +0100297 ARM_COMPUTE_RETURN_ERROR_ON_MSG_VAR(success == false, "Unsupported kernel size: %d x %d.\n", kernel_shape.n_rows, kernel_shape.n_cols);
298 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using input transform: %s\n", winograd_impl.input_transform->get_name().c_str());
299 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using weight transform: %s\n", winograd_impl.input_transform->get_name().c_str());
300 ARM_COMPUTE_LOG_MSG_WITH_FORMAT_ACL(arm_compute::logging::LogLevel::INFO, "Using output transform: %s\n", winograd_impl.input_transform->get_name().c_str());
301 return Status{};
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100302}
303
304void CpuWinogradConv2d::run(ITensorPack &tensors)
305{
306 prepare(tensors);
ramelg01a1f78512022-06-29 16:28:10 +0100307 auto src = tensors.get_const_tensor(ACL_SRC_0);
308 auto biases = tensors.get_const_tensor(ACL_SRC_2);
309 auto output = tensors.get_tensor(ACL_DST);
310 Window win;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100311
ramelg01a1f78512022-06-29 16:28:10 +0100312 const uint32_t nthreads = NEScheduler::get().num_threads();
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100313
ramelg01a1f78512022-06-29 16:28:10 +0100314 // The Winograd transform implementation does fine-grain threading inside the transforms. Just pass thread_id and nthreads.
315 win.set(Window::DimX, Window::Dimension(0, nthreads, 1));
316
317 // Wrap the winograd-domain tensorInfos created in configuration in tensors and allocate the required memory.
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100318 CpuAuxTensorHandler input_nhwc(offset_int_vec(PermutedInput), _input_nhwc, tensors, true);
ramelg01a1f78512022-06-29 16:28:10 +0100319 CpuAuxTensorHandler winograd_input_transformed(offset_int_vec(TransformedInput), _winograd_transformed_input, tensors, true);
Georgios Pinitas87a74ef2021-08-20 17:26:45 +0100320 CpuAuxTensorHandler input_workspace(offset_int_vec(WorkspaceIO), _input_workspace, tensors, true);
ramelg01a1f78512022-06-29 16:28:10 +0100321 const bool is_nchw = _data_layout == DataLayout::NCHW;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100322 if(is_nchw)
323 {
324 //Bring channels to the front as Winograd code expects the tensor to be in the format NHWC
ramelg01a1f78512022-06-29 16:28:10 +0100325 ITensorPack pack{ { ACL_SRC, src }, { ACL_DST, input_nhwc.get() } };
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100326 _permute_input->run(pack);
327 }
328
ramelg01a1f78512022-06-29 16:28:10 +0100329 CpuAuxTensorHandler winograd_output_transformed(offset_int_vec(TransformedOutput), _winograd_transformed_output, tensors, true);
330 CpuAuxTensorHandler output_workspace(offset_int_vec(WorkspaceIO), _output_workspace, tensors, true);
331 CpuAuxTensorHandler output_nhwc(offset_int_vec(PermutedOutput), _output_nhwc, tensors, true);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100332
ramelg01a1f78512022-06-29 16:28:10 +0100333 ITensorPack transform_input_pack{ { ACL_SRC, is_nchw ? input_nhwc.get() : src }, { ACL_DST, winograd_input_transformed.get() }, { ACL_INT, input_workspace.get() } };
334 _transform_input_kernel = std::make_unique<CpuWinogradConv2dTransformInputKernel>(_winograd_impl, *_conv_args, nthreads);
335
336 NEScheduler::get().schedule_op(_transform_input_kernel.get(), Window::DimX, win, transform_input_pack);
337
338 CpuAuxTensorHandler winograd_weights_transformed(offset_int_vec(TransformedWeights), _winograd_transformed_weights, tensors, true);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100339
340 // Run 16 GEMMs in multiple threads, each kernel runs one or more GEMMs
Georgios Pinitas87a74ef2021-08-20 17:26:45 +0100341 ITensorPack gemm_pack = tensors;
ramelg01a1f78512022-06-29 16:28:10 +0100342 gemm_pack.add_const_tensor(ACL_SRC, winograd_input_transformed.get());
343 gemm_pack.add_const_tensor(ACL_SRC_1, winograd_weights_transformed.get());
Georgios Pinitas87a74ef2021-08-20 17:26:45 +0100344 gemm_pack.add_const_tensor(ACL_BIAS, nullptr);
ramelg01a1f78512022-06-29 16:28:10 +0100345 gemm_pack.add_tensor(ACL_DST, winograd_output_transformed.get());
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100346 _gemm_function->run(gemm_pack);
347
ramelg01a1f78512022-06-29 16:28:10 +0100348 // Output transform
349 _transform_output_kernel = std::make_unique<CpuWinogradConv2dTransformOutputKernel>(_winograd_impl, *_conv_args, nthreads);
350 ITensorPack transform_output_pack{ { ACL_SRC_0, winograd_output_transformed.get() }, { ACL_DST, is_nchw ? output_nhwc.get() : output }, { ACL_SRC_1, biases }, { ACL_INT, output_workspace.get() } };
351 NEScheduler::get().schedule_op(_transform_output_kernel.get(), Window::DimX, win, transform_output_pack);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100352 if(is_nchw)
353 {
354 // Reorder the convoluted output to ACL's ordering NCHW
ramelg01a1f78512022-06-29 16:28:10 +0100355 ITensorPack pack{ { ACL_SRC, output_nhwc.get() }, { ACL_DST, output } };
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100356 _permute_output->run(pack);
357 }
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100358 if(_run_activation)
359 {
ramelg01a1f78512022-06-29 16:28:10 +0100360 ITensorPack pack{ { ACL_SRC, output }, { ACL_DST, output } };
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100361 _activation_func->run(pack);
362 }
363}
364
365void CpuWinogradConv2d::prepare(ITensorPack &tensors)
366{
367 if(!_is_prepared)
368 {
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100369 const ITensor *weights = tensors.get_const_tensor(ACL_SRC_1);
370 ITensor *weights_aux = utils::cast::polymorphic_cast<ITensor *>(tensors.get_tensor(offset_int_vec(PermutedWeights)));
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100371
372 CpuAuxTensorHandler permuted_weights(_weights_hwio, *weights_aux);
373 ITensorPack permute_tensors{ { ACL_SRC, weights }, { ACL_DST, permuted_weights.get() } };
374 _permute_weights->run(permute_tensors);
ramelg01a1f78512022-06-29 16:28:10 +0100375 const int element_size_in_bytes = permuted_weights.get()->info()->element_size();
376 // Weights were in OHWI format, before being permuted "permuted_weights" to be in HWIO format.
377 const unsigned int height_idx = 3; // H in HWIO
378 const unsigned int width_idx = 2; // W in HWIO
379 const unsigned int channel_idx = 1; // I in HWIO
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100380
ramelg01a1f78512022-06-29 16:28:10 +0100381 const int permuted_weight_row_stride = permuted_weights.get()->info()->strides_in_bytes()[height_idx] / element_size_in_bytes;
382 const int permuted_weight_col_stride = permuted_weights.get()->info()->strides_in_bytes()[width_idx] / element_size_in_bytes;
383 const int permuted_weight_channel_stride = permuted_weights.get()->info()->strides_in_bytes()[channel_idx] / element_size_in_bytes;
384
385 // Wrap the winograd-domain transformed weight TensorInfo in Auxiliary tensor and allocate the required memory.
Georgios Pinitas87a74ef2021-08-20 17:26:45 +0100386 ITensor *weights_transf = utils::cast::polymorphic_cast<ITensor *>(tensors.get_tensor(offset_int_vec(TransformedWeights)));
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100387 ARM_COMPUTE_ERROR_ON_NULLPTR(weights_transf);
ramelg01a1f78512022-06-29 16:28:10 +0100388 CpuAuxTensorHandler winograd_transformed_weights(_winograd_transformed_weights, *weights_transf);
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100389
ramelg01a1f78512022-06-29 16:28:10 +0100390 const void *permuted_weights_ptr;
391 void *win_wght_transf_ptr;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100392
ramelg01a1f78512022-06-29 16:28:10 +0100393 permuted_weights_ptr = reinterpret_cast<const void *>(permuted_weights.get()->buffer() + permuted_weights.get()->info()->offset_first_element_in_bytes());
394 win_wght_transf_ptr = reinterpret_cast<void *>(winograd_transformed_weights.get()->buffer() + winograd_transformed_weights.get()->info()->offset_first_element_in_bytes());
395
396 // Prepare Weights
397 _winograd_impl.weight_transform->execute(
398 *_conv_args,
399 permuted_weights_ptr,
400 permuted_weight_row_stride,
401 permuted_weight_col_stride,
402 permuted_weight_channel_stride,
403 win_wght_transf_ptr,
404 _winograd_impl.winograd_spec,
405 0, 1 // Thread 1 of 1
406 );
Georgios Pinitas66341942021-07-30 12:21:07 +0100407 ITensorPack gemm_pack = tensors;
ramelg01a1f78512022-06-29 16:28:10 +0100408 gemm_pack.add_const_tensor(ACL_SRC_1, winograd_transformed_weights.get());
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100409 _gemm_function->prepare(gemm_pack);
ramelg01a1f78512022-06-29 16:28:10 +0100410 _is_prepared = 1;
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100411 }
412}
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100413experimental::MemoryRequirements CpuWinogradConv2d::workspace() const
414{
415 return _aux_mem;
416}
ramelg01a1f78512022-06-29 16:28:10 +0100417
Michalis Spyrou96f977e2021-07-01 12:20:56 +0100418} // namespace cpu
ramelg01a1f78512022-06-29 16:28:10 +0100419} // namespace arm_compute