ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 1 | /* |
Viet-Hoa Do | bb1ab05 | 2022-12-23 14:48:33 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2022 Arm Limited. |
ramelg01 | a1f7851 | 2022-06-29 16:28:10 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #if __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) |
| 26 | #include <cstddef> |
| 27 | |
| 28 | namespace arm_conv { |
| 29 | namespace winograd { |
| 30 | namespace input_transform { |
| 31 | |
| 32 | void sve_fp32_6x6( |
| 33 | const unsigned int num_channels, |
| 34 | const float *input, |
| 35 | const size_t input_row_stride, |
| 36 | const size_t input_col_stride, |
| 37 | float *output, |
| 38 | const size_t output_col_stride |
| 39 | ) |
| 40 | { |
| 41 | const float B_values[4] = { 1.0f, 2.0f, 4.0f, 5.0f }; |
| 42 | long long_channels = num_channels; |
| 43 | |
| 44 | // Generated by armasmgen (February 04th, 2021) |
| 45 | __asm__ __volatile__( |
| 46 | "fmov z16.s, #4.0\n" |
| 47 | "ptrue p1.b\n" |
| 48 | "ld1rqw { z2.s }, p1/Z, [%x[B_values]]\n" |
| 49 | "add x16, %x[input_row_0], %x[input_row_stride], LSL #2\n" |
| 50 | "add x15, %x[output_row_0], %x[output_row_stride], LSL #2\n" |
| 51 | "add x14, %x[input_row_0], %x[input_row_stride], LSL #3\n" |
| 52 | "add x13, %x[output_row_0], %x[output_row_stride], LSL #3\n" |
| 53 | "add x12, x14, %x[input_row_stride], LSL #2\n" |
| 54 | "add x11, x13, %x[output_row_stride], LSL #2\n" |
| 55 | "add x10, %x[input_row_0], %x[input_row_stride], LSL #4\n" |
| 56 | "add x9, %x[output_row_0], %x[output_row_stride], LSL #4\n" |
| 57 | "add x28, x10, %x[input_row_stride], LSL #2\n" |
| 58 | "add x27, x9, %x[output_row_stride], LSL #2\n" |
| 59 | "lsl x26, %x[input_col_1_stride], #0x1\n" |
| 60 | "lsl x25, %x[output_col_1_stride], #0x1\n" |
| 61 | "add x24, x26, %x[input_col_1_stride]\n" |
| 62 | "add x23, x25, %x[output_col_1_stride]\n" |
| 63 | "lsl x22, %x[input_col_1_stride], #0x2\n" |
| 64 | "lsl x21, %x[output_col_1_stride], #0x2\n" |
| 65 | "add x20, x22, %x[input_col_1_stride]\n" |
| 66 | "add x19, x21, %x[output_col_1_stride]\n" |
| 67 | "whilelt p0.s, XZR, %x[num_channels]\n" |
| 68 | "beq 2f\n" |
| 69 | "1:" // channel_loop |
| 70 | "ld1w { z31.s }, p0/Z, [%x[input_row_0]]\n" |
| 71 | "decw %x[num_channels]\n" |
| 72 | "ld1w { z28.s }, p0/Z, [%x[input_row_0], %x[input_col_1_stride], LSL #2]\n" |
| 73 | "fmul z13.s, z28.s, z2.s[1]\n" |
| 74 | "ld1w { z27.s }, p0/Z, [%x[input_row_0], x26, LSL #2]\n" |
| 75 | "ld1w { z11.s }, p0/Z, [%x[input_row_0], x24, LSL #2]\n" |
| 76 | "fneg z13.s, p1/M, z13.s\n" |
| 77 | "ld1w { z7.s }, p0/Z, [%x[input_row_0], x22, LSL #2]\n" |
| 78 | "fsub z15.s, z7.s, z27.s\n" |
| 79 | "fmad z31.s, p1/M, z16.s, z7.s\n" |
| 80 | "ld1w { z3.s }, p0/Z, [%x[input_row_0], x20, LSL #2]\n" |
| 81 | "fmla z13.s, z11.s, z2.s[1]\n" |
| 82 | "ld1w { z12.s }, p0/Z, [x14]\n" |
| 83 | "incb %x[input_row_0]\n" |
| 84 | "fmls z31.s, z27.s, z2.s[3]\n" |
| 85 | "ld1w { z14.s }, p0/Z, [x14, %x[input_col_1_stride], LSL #2]\n" |
| 86 | "fsub z25.s, z15.s, z13.s\n" |
| 87 | "fadd z8.s, z13.s, z15.s\n" |
| 88 | "ld1w { z24.s }, p0/Z, [x14, x26, LSL #2]\n" |
| 89 | "fmsb z27.s, p1/M, z16.s, z7.s\n" |
| 90 | "ld1w { z22.s }, p0/Z, [x14, x24, LSL #2]\n" |
| 91 | "fmul z7.s, z28.s, z2.s[2]\n" |
| 92 | "ld1w { z1.s }, p0/Z, [x14, x22, LSL #2]\n" |
| 93 | "fsub z15.s, z1.s, z24.s\n" |
| 94 | "fneg z7.s, p1/M, z7.s\n" |
| 95 | "ld1w { z20.s }, p0/Z, [x14, x20, LSL #2]\n" |
| 96 | "fadd z7.s, z7.s, z11.s\n" |
| 97 | "ld1w { z29.s }, p0/Z, [x10]\n" |
| 98 | "incb x14\n" |
| 99 | "fmad z28.s, p1/M, z16.s, z3.s\n" |
| 100 | "ld1w { z10.s }, p0/Z, [x10, %x[input_col_1_stride], LSL #2]\n" |
| 101 | "fmad z12.s, p1/M, z16.s, z1.s\n" |
| 102 | "ld1w { z18.s }, p0/Z, [x10, x26, LSL #2]\n" |
| 103 | "fmul z13.s, z14.s, z2.s[1]\n" |
| 104 | "ld1w { z19.s }, p0/Z, [x10, x24, LSL #2]\n" |
| 105 | "fadd z17.s, z7.s, z27.s\n" |
| 106 | "ld1w { z9.s }, p0/Z, [x10, x22, LSL #2]\n" |
| 107 | "fsub z27.s, z27.s, z7.s\n" |
| 108 | "fmls z28.s, z11.s, z2.s[3]\n" |
| 109 | "ld1w { z21.s }, p0/Z, [x10, x20, LSL #2]\n" |
| 110 | "incb x10\n" |
| 111 | "fmls z12.s, z24.s, z2.s[3]\n" |
| 112 | "fneg z13.s, p1/M, z13.s\n" |
| 113 | "fmla z13.s, z22.s, z2.s[1]\n" |
| 114 | "fsub z30.s, z15.s, z13.s\n" |
| 115 | "fadd z4.s, z13.s, z15.s\n" |
| 116 | "fmsb z24.s, p1/M, z16.s, z1.s\n" |
| 117 | "fsub z15.s, z9.s, z18.s\n" |
| 118 | "fmul z1.s, z14.s, z2.s[2]\n" |
| 119 | "fmad z14.s, p1/M, z16.s, z20.s\n" |
| 120 | "fmad z29.s, p1/M, z16.s, z9.s\n" |
| 121 | "fmul z13.s, z10.s, z2.s[1]\n" |
| 122 | "fneg z1.s, p1/M, z1.s\n" |
| 123 | "fadd z1.s, z1.s, z22.s\n" |
| 124 | "fmls z14.s, z22.s, z2.s[3]\n" |
| 125 | "fmls z29.s, z18.s, z2.s[3]\n" |
| 126 | "fadd z5.s, z1.s, z24.s\n" |
| 127 | "fsub z24.s, z24.s, z1.s\n" |
| 128 | "fneg z13.s, p1/M, z13.s\n" |
| 129 | "fmla z13.s, z19.s, z2.s[1]\n" |
| 130 | "fsub z23.s, z15.s, z13.s\n" |
| 131 | "fadd z11.s, z13.s, z15.s\n" |
| 132 | "fmsb z18.s, p1/M, z16.s, z9.s\n" |
| 133 | "fmul z9.s, z10.s, z2.s[2]\n" |
| 134 | "fmad z10.s, p1/M, z16.s, z21.s\n" |
| 135 | "fmad z31.s, p1/M, z16.s, z29.s\n" |
| 136 | "fmad z8.s, p1/M, z16.s, z11.s\n" |
| 137 | "fneg z9.s, p1/M, z9.s\n" |
| 138 | "fadd z9.s, z9.s, z19.s\n" |
| 139 | "fmls z10.s, z19.s, z2.s[3]\n" |
| 140 | "fmls z31.s, z12.s, z2.s[3]\n" |
| 141 | "st1w { z31.s }, p0, [%x[output_row_0]]\n" |
| 142 | "fadd z26.s, z9.s, z18.s\n" |
| 143 | "fsub z18.s, z18.s, z9.s\n" |
| 144 | "fmls z8.s, z4.s, z2.s[3]\n" |
| 145 | "fmad z25.s, p1/M, z16.s, z23.s\n" |
| 146 | "fmad z28.s, p1/M, z16.s, z10.s\n" |
| 147 | "fmad z17.s, p1/M, z16.s, z26.s\n" |
| 148 | "fmad z27.s, p1/M, z16.s, z18.s\n" |
| 149 | "fmls z25.s, z30.s, z2.s[3]\n" |
| 150 | "fmls z28.s, z14.s, z2.s[3]\n" |
| 151 | "fmls z17.s, z5.s, z2.s[3]\n" |
| 152 | "st1w { z17.s }, p0, [%x[output_row_0], %x[output_col_1_stride], LSL #2]\n" |
| 153 | "fmls z27.s, z24.s, z2.s[3]\n" |
| 154 | "st1w { z27.s }, p0, [%x[output_row_0], x25, LSL #2]\n" |
| 155 | "st1w { z8.s }, p0, [%x[output_row_0], x23, LSL #2]\n" |
| 156 | "st1w { z25.s }, p0, [%x[output_row_0], x21, LSL #2]\n" |
| 157 | "st1w { z28.s }, p0, [%x[output_row_0], x19, LSL #2]\n" |
| 158 | "incb %x[output_row_0]\n" |
| 159 | "ld1w { z19.s }, p0/Z, [x16]\n" |
| 160 | "ld1w { z7.s }, p0/Z, [x16, %x[input_col_1_stride], LSL #2]\n" |
| 161 | "fmul z13.s, z7.s, z2.s[1]\n" |
| 162 | "ld1w { z6.s }, p0/Z, [x16, x26, LSL #2]\n" |
| 163 | "ld1w { z27.s }, p0/Z, [x16, x24, LSL #2]\n" |
| 164 | "fneg z13.s, p1/M, z13.s\n" |
| 165 | "ld1w { z25.s }, p0/Z, [x16, x22, LSL #2]\n" |
| 166 | "fsub z15.s, z25.s, z6.s\n" |
| 167 | "fmad z19.s, p1/M, z16.s, z25.s\n" |
| 168 | "ld1w { z20.s }, p0/Z, [x16, x20, LSL #2]\n" |
| 169 | "fmla z13.s, z27.s, z2.s[1]\n" |
| 170 | "ld1w { z0.s }, p0/Z, [x12]\n" |
| 171 | "incb x16\n" |
| 172 | "fmls z19.s, z6.s, z2.s[3]\n" |
| 173 | "ld1w { z31.s }, p0/Z, [x12, %x[input_col_1_stride], LSL #2]\n" |
| 174 | "fsub z8.s, z15.s, z13.s\n" |
| 175 | "fadd z28.s, z13.s, z15.s\n" |
| 176 | "ld1w { z1.s }, p0/Z, [x12, x26, LSL #2]\n" |
| 177 | "fmsb z6.s, p1/M, z16.s, z25.s\n" |
| 178 | "ld1w { z21.s }, p0/Z, [x12, x24, LSL #2]\n" |
| 179 | "fmul z25.s, z7.s, z2.s[2]\n" |
| 180 | "ld1w { z22.s }, p0/Z, [x12, x22, LSL #2]\n" |
| 181 | "fsub z15.s, z22.s, z1.s\n" |
| 182 | "fneg z25.s, p1/M, z25.s\n" |
| 183 | "ld1w { z17.s }, p0/Z, [x12, x20, LSL #2]\n" |
| 184 | "fadd z25.s, z25.s, z27.s\n" |
| 185 | "incb x12\n" |
| 186 | "fmad z7.s, p1/M, z16.s, z20.s\n" |
| 187 | "fmad z0.s, p1/M, z16.s, z22.s\n" |
| 188 | "fmul z13.s, z31.s, z2.s[1]\n" |
| 189 | "fadd z3.s, z25.s, z6.s\n" |
| 190 | "fsub z6.s, z6.s, z25.s\n" |
| 191 | "fmls z7.s, z27.s, z2.s[3]\n" |
| 192 | "fmls z0.s, z1.s, z2.s[3]\n" |
| 193 | "fneg z13.s, p1/M, z13.s\n" |
| 194 | "fmla z13.s, z21.s, z2.s[1]\n" |
| 195 | "fsub z9.s, z15.s, z13.s\n" |
| 196 | "fadd z27.s, z13.s, z15.s\n" |
| 197 | "fmsb z1.s, p1/M, z16.s, z22.s\n" |
| 198 | "fsub z15.s, z29.s, z12.s\n" |
| 199 | "fmul z22.s, z31.s, z2.s[2]\n" |
| 200 | "fmad z31.s, p1/M, z16.s, z17.s\n" |
| 201 | "fmul z13.s, z19.s, z2.s[1]\n" |
| 202 | "fmsb z12.s, p1/M, z16.s, z29.s\n" |
| 203 | "fneg z22.s, p1/M, z22.s\n" |
| 204 | "fadd z22.s, z22.s, z21.s\n" |
| 205 | "fmls z31.s, z21.s, z2.s[3]\n" |
| 206 | "fneg z13.s, p1/M, z13.s\n" |
| 207 | "fadd z25.s, z22.s, z1.s\n" |
| 208 | "fsub z1.s, z1.s, z22.s\n" |
| 209 | "fmla z13.s, z0.s, z2.s[1]\n" |
| 210 | "fmul z29.s, z19.s, z2.s[2]\n" |
| 211 | "fadd z22.s, z13.s, z15.s\n" |
| 212 | "st1w { z22.s }, p0, [x11]\n" |
| 213 | "fneg z29.s, p1/M, z29.s\n" |
| 214 | "fsub z22.s, z15.s, z13.s\n" |
| 215 | "fadd z29.s, z29.s, z0.s\n" |
| 216 | "st1w { z22.s }, p0, [x9]\n" |
| 217 | "fadd z22.s, z29.s, z12.s\n" |
| 218 | "fsub z15.s, z26.s, z5.s\n" |
| 219 | "fmul z13.s, z3.s, z2.s[1]\n" |
| 220 | "fsub z12.s, z12.s, z29.s\n" |
| 221 | "fmsb z5.s, p1/M, z16.s, z26.s\n" |
| 222 | "fmul z26.s, z3.s, z2.s[2]\n" |
| 223 | "fneg z13.s, p1/M, z13.s\n" |
| 224 | "fmla z13.s, z25.s, z2.s[1]\n" |
| 225 | "fneg z26.s, p1/M, z26.s\n" |
| 226 | "fadd z26.s, z26.s, z25.s\n" |
| 227 | "fadd z21.s, z13.s, z15.s\n" |
| 228 | "st1w { z21.s }, p0, [x11, %x[output_col_1_stride], LSL #2]\n" |
| 229 | "fsub z21.s, z15.s, z13.s\n" |
| 230 | "fmul z13.s, z6.s, z2.s[1]\n" |
| 231 | "fneg z13.s, p1/M, z13.s\n" |
| 232 | "st1w { z21.s }, p0, [x9, %x[output_col_1_stride], LSL #2]\n" |
| 233 | "fadd z21.s, z26.s, z5.s\n" |
| 234 | "fsub z15.s, z18.s, z24.s\n" |
| 235 | "fmla z13.s, z1.s, z2.s[1]\n" |
| 236 | "fsub z5.s, z5.s, z26.s\n" |
| 237 | "fmsb z24.s, p1/M, z16.s, z18.s\n" |
| 238 | "fmul z18.s, z6.s, z2.s[2]\n" |
| 239 | "fadd z20.s, z13.s, z15.s\n" |
| 240 | "st1w { z20.s }, p0, [x11, x25, LSL #2]\n" |
| 241 | "fneg z18.s, p1/M, z18.s\n" |
| 242 | "fsub z20.s, z15.s, z13.s\n" |
| 243 | "fadd z18.s, z18.s, z1.s\n" |
| 244 | "st1w { z20.s }, p0, [x9, x25, LSL #2]\n" |
| 245 | "fadd z20.s, z18.s, z24.s\n" |
| 246 | "fsub z15.s, z11.s, z4.s\n" |
| 247 | "fmul z13.s, z28.s, z2.s[1]\n" |
| 248 | "fsub z24.s, z24.s, z18.s\n" |
| 249 | "fmsb z4.s, p1/M, z16.s, z11.s\n" |
| 250 | "fmul z11.s, z28.s, z2.s[2]\n" |
| 251 | "fneg z13.s, p1/M, z13.s\n" |
| 252 | "fmla z13.s, z27.s, z2.s[1]\n" |
| 253 | "fneg z11.s, p1/M, z11.s\n" |
| 254 | "fadd z11.s, z11.s, z27.s\n" |
| 255 | "fadd z26.s, z13.s, z15.s\n" |
| 256 | "st1w { z26.s }, p0, [x11, x23, LSL #2]\n" |
| 257 | "fsub z26.s, z15.s, z13.s\n" |
| 258 | "fmul z13.s, z8.s, z2.s[1]\n" |
| 259 | "fneg z13.s, p1/M, z13.s\n" |
| 260 | "st1w { z26.s }, p0, [x9, x23, LSL #2]\n" |
| 261 | "fadd z26.s, z11.s, z4.s\n" |
| 262 | "fsub z15.s, z23.s, z30.s\n" |
| 263 | "fmla z13.s, z9.s, z2.s[1]\n" |
| 264 | "fsub z4.s, z4.s, z11.s\n" |
| 265 | "fmsb z30.s, p1/M, z16.s, z23.s\n" |
| 266 | "fmul z23.s, z8.s, z2.s[2]\n" |
| 267 | "fadd z18.s, z13.s, z15.s\n" |
| 268 | "st1w { z18.s }, p0, [x11, x21, LSL #2]\n" |
| 269 | "fneg z23.s, p1/M, z23.s\n" |
| 270 | "fsub z18.s, z15.s, z13.s\n" |
| 271 | "fadd z23.s, z23.s, z9.s\n" |
| 272 | "st1w { z18.s }, p0, [x9, x21, LSL #2]\n" |
| 273 | "fadd z18.s, z23.s, z30.s\n" |
| 274 | "fsub z15.s, z10.s, z14.s\n" |
| 275 | "fmul z13.s, z7.s, z2.s[1]\n" |
| 276 | "fsub z30.s, z30.s, z23.s\n" |
| 277 | "fmsb z14.s, p1/M, z16.s, z10.s\n" |
| 278 | "fmul z10.s, z7.s, z2.s[2]\n" |
| 279 | "fneg z13.s, p1/M, z13.s\n" |
| 280 | "fmla z13.s, z31.s, z2.s[1]\n" |
| 281 | "fneg z10.s, p1/M, z10.s\n" |
| 282 | "fadd z10.s, z10.s, z31.s\n" |
| 283 | "fadd z17.s, z13.s, z15.s\n" |
| 284 | "st1w { z17.s }, p0, [x11, x19, LSL #2]\n" |
| 285 | "fsub z17.s, z15.s, z13.s\n" |
| 286 | "incb x11\n" |
| 287 | "st1w { z17.s }, p0, [x9, x19, LSL #2]\n" |
| 288 | "fadd z17.s, z10.s, z14.s\n" |
| 289 | "fsub z14.s, z14.s, z10.s\n" |
| 290 | "st1w { z22.s }, p0, [x15]\n" |
| 291 | "incb x9\n" |
| 292 | "st1w { z12.s }, p0, [x13]\n" |
| 293 | "st1w { z21.s }, p0, [x15, %x[output_col_1_stride], LSL #2]\n" |
| 294 | "st1w { z5.s }, p0, [x13, %x[output_col_1_stride], LSL #2]\n" |
| 295 | "st1w { z20.s }, p0, [x15, x25, LSL #2]\n" |
| 296 | "st1w { z24.s }, p0, [x13, x25, LSL #2]\n" |
| 297 | "st1w { z26.s }, p0, [x15, x23, LSL #2]\n" |
| 298 | "st1w { z4.s }, p0, [x13, x23, LSL #2]\n" |
| 299 | "st1w { z18.s }, p0, [x15, x21, LSL #2]\n" |
| 300 | "st1w { z30.s }, p0, [x13, x21, LSL #2]\n" |
| 301 | "st1w { z17.s }, p0, [x15, x19, LSL #2]\n" |
| 302 | "incb x15\n" |
| 303 | "st1w { z14.s }, p0, [x13, x19, LSL #2]\n" |
| 304 | "incb x13\n" |
| 305 | "ld1w { z23.s }, p0/Z, [x28]\n" |
| 306 | "ld1w { z22.s }, p0/Z, [x28, %x[input_col_1_stride], LSL #2]\n" |
| 307 | "fmul z13.s, z22.s, z2.s[1]\n" |
| 308 | "ld1w { z21.s }, p0/Z, [x28, x26, LSL #2]\n" |
| 309 | "ld1w { z20.s }, p0/Z, [x28, x24, LSL #2]\n" |
| 310 | "fneg z13.s, p1/M, z13.s\n" |
| 311 | "ld1w { z26.s }, p0/Z, [x28, x22, LSL #2]\n" |
| 312 | "fsub z15.s, z26.s, z21.s\n" |
| 313 | "fmad z23.s, p1/M, z16.s, z26.s\n" |
| 314 | "ld1w { z18.s }, p0/Z, [x28, x20, LSL #2]\n" |
| 315 | "fmla z13.s, z20.s, z2.s[1]\n" |
| 316 | "incb x28\n" |
| 317 | "fmls z23.s, z21.s, z2.s[3]\n" |
| 318 | "fsub z17.s, z15.s, z13.s\n" |
| 319 | "fadd z30.s, z13.s, z15.s\n" |
| 320 | "fmsb z21.s, p1/M, z16.s, z26.s\n" |
| 321 | "fmul z26.s, z22.s, z2.s[2]\n" |
| 322 | "fmad z22.s, p1/M, z16.s, z18.s\n" |
| 323 | "fmad z19.s, p1/M, z16.s, z23.s\n" |
| 324 | "fmad z28.s, p1/M, z16.s, z30.s\n" |
| 325 | "fneg z26.s, p1/M, z26.s\n" |
| 326 | "fadd z26.s, z26.s, z20.s\n" |
| 327 | "fmls z22.s, z20.s, z2.s[3]\n" |
| 328 | "fmls z19.s, z0.s, z2.s[3]\n" |
| 329 | "st1w { z19.s }, p0, [x27]\n" |
| 330 | "fadd z23.s, z26.s, z21.s\n" |
| 331 | "fsub z21.s, z21.s, z26.s\n" |
| 332 | "fmls z28.s, z27.s, z2.s[3]\n" |
| 333 | "fmad z8.s, p1/M, z16.s, z17.s\n" |
| 334 | "fmad z7.s, p1/M, z16.s, z22.s\n" |
| 335 | "fmad z3.s, p1/M, z16.s, z23.s\n" |
| 336 | "fmad z6.s, p1/M, z16.s, z21.s\n" |
| 337 | "fmls z8.s, z9.s, z2.s[3]\n" |
| 338 | "fmls z7.s, z31.s, z2.s[3]\n" |
| 339 | "fmls z3.s, z25.s, z2.s[3]\n" |
| 340 | "st1w { z3.s }, p0, [x27, %x[output_col_1_stride], LSL #2]\n" |
| 341 | "fmls z6.s, z1.s, z2.s[3]\n" |
| 342 | "st1w { z6.s }, p0, [x27, x25, LSL #2]\n" |
| 343 | "st1w { z28.s }, p0, [x27, x23, LSL #2]\n" |
| 344 | "st1w { z8.s }, p0, [x27, x21, LSL #2]\n" |
| 345 | "st1w { z7.s }, p0, [x27, x19, LSL #2]\n" |
| 346 | "incb x27\n" |
| 347 | "whilelt p0.s, XZR, %x[num_channels]\n" |
| 348 | "bne 1b\n" |
| 349 | "2:" // channel_loop_end |
| 350 | |
| 351 | : [input_row_0] "+&r" (input), [num_channels] "+&r" (long_channels), [output_row_0] "+&r" (output) |
| 352 | : [B_values] "r" (B_values), [input_col_1_stride] "r" ((long) input_col_stride), [input_row_stride] "r" ((long) input_row_stride), [output_col_1_stride] "r" ((long) output_col_stride), [output_row_stride] "r" (6 * (long) output_col_stride) |
| 353 | : "cc", "memory", "p0", "p1", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" |
| 354 | ); |
| 355 | } |
| 356 | |
| 357 | } // namespace input_transform |
| 358 | } // namespace winograd |
| 359 | } // namespace arm_conv |
| 360 | |
| 361 | #endif // __aarch64__ && defined(ARM_COMPUTE_ENABLE_SVE) |