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Sheri Zhang1efed922021-03-10 22:43:38 +00001/*
2 * Copyright (c) 2017-2021 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24#ifndef ARM_COMPUTE_CL_DIRECT_CONVOLUTION_KERNEL_H
25#define ARM_COMPUTE_CL_DIRECT_CONVOLUTION_KERNEL_H
26
27#include "src/core/common/Macros.h"
28#include "src/core/gpu/cl/ClCompileContext.h"
29#include "src/core/gpu/cl/IClKernel.h"
30
31namespace arm_compute
32{
33namespace opencl
34{
35namespace kernels
36{
37/** Interface for the direct convolution kernel.
38 */
Teresa Charlin91b7f742021-04-12 13:57:00 +010039class ClDirectConvolutionKernel : public IClKernel
Sheri Zhang1efed922021-03-10 22:43:38 +000040{
41public:
42 ClDirectConvolutionKernel() = default;
43 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(ClDirectConvolutionKernel);
44 /** Set the src, weights, biases and dst tensors info.
45 *
46 * @note: Due to set_valid_region(), thus src/weights/biases cannot be const. Need to change this once the set_valid_region() is removed.
47 *
48 * @note: DirectConvolution only works in the following configurations:
49 * 1x1 convolution with stride_x = 1/2/3, stride_y = 1/2/3
50 * 3x3 convolution with stride_x = 1/2, stride_y = 1/2
51 * 5x5 convolution with stride_x = 1/2, stride_y = 1/2
52 * 9x9 convolution with stride_x = 1/2, stride_y = 1/2
53 *
54 * @param[in] compile_context The compile context to be used.
55 * @param[in] src The src tensor info to convolve. 3 lower dimensions represent a single src [width, height, IFM],
56 * while every optional dimension from 4 and above represent a batch of inputs. Data types supported: QASYMM8_SIGNED/QASYMM8/F16/F32.
57 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM].
58 * The 3rd dimension must be the same as the src's volume 3rd dimension.
59 * Data type supported:Same as @p src.
60 * @param[in] biases Biases tensor info. Biases are 1D tensor with dimension [OFM].
61 * Data type supported: Should match @p src data type, except for src of QASYMM8 and QASYMM8_SIGNED type where biases should be of S32 type
62 * @param[out] dst Output tensor info.
63 * The 3rd dimensions must be equal to the 4th dimension of the @p kernels tensor. Data types supported: Same as @p src.
64 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
65 */
66 void configure(const CLCompileContext &compile_context, ITensorInfo *src, ITensorInfo *weights, ITensorInfo *biases, ITensorInfo *dst, const PadStrideInfo &conv_info);
67 /** Static function to check if given info will lead to a valid configuration of @ref ClDirectConvolutionKernel
68 *
69 * @param[in] src The src tensor info to convolve. 3 lower dimensions represent a single src [width, height, IFM],
70 * while every optional dimension from 4 and above represent a batch of inputs. Data types supported: QASYMM8_SIGNED/QASYMM8/F16/F32.
71 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM].
72 * The 3rd dimension must be the same as the src's volume 3rd dimension.
73 * Data type supported:Same as @p src.
74 * @param[in] biases Biases tensor info. Biases are 1D tensor with dimension [OFM].
75 * Data type supported: Should match @p src data type, except for src of QASYMM8 and QASYMM8_SIGNED type where biases should be of S32 type.
76 * @param[in] dst Output tensor info.
77 * The 3rd dimensions must be equal to the 4th dimension of the @p kernels tensor. Data types supported: Same as @p src.
78 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
79 * @param[in] target Target GPU architecture.
80 *
81 * @return a status
82 */
83 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const PadStrideInfo &conv_info, const GPUTarget target);
84
85 // Inherited methods overridden:
86 void run_op(ITensorPack &tensors, const Window &window, cl::CommandQueue &queue) override;
87 BorderSize border_size() const override;
88
89public:
90 DataLayout _data_layout{};
91 BorderSize _border_size{};
92 PadStrideInfo _conv_info{};
93};
94} // namespace kernels
95} // namespace opencl
96} // namespace arm_compute
97#endif /*ARM_COMPUTE_CL_DIRECT_CONVOLUTION_KERNEL_H */