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Gian Marco Iodice781cba72020-06-19 16:56:57 +01001/*
SiCongLi1af54162021-10-06 15:25:57 +01002 * Copyright (c) 2020-2021 Arm Limited.
Gian Marco Iodice781cba72020-06-19 16:56:57 +01003 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
SiCongLi1af54162021-10-06 15:25:57 +010024#include "arm_compute/core/CL/CLCompileContext.h"
Gian Marco Iodice781cba72020-06-19 16:56:57 +010025#include "arm_compute/core/Error.h"
26#include "arm_compute/core/Types.h"
SiCongLi1af54162021-10-06 15:25:57 +010027#include "arm_compute/core/Validate.h"
28#include "support/StringSupport.h"
Gian Marco Iodice781cba72020-06-19 16:56:57 +010029
30#include "src/core/CL/CLUtils.h"
SiCongLid5694c92021-11-12 17:33:45 +000031#include "src/core/experimental/PostOpUtils.h"
Gian Marco Iodice781cba72020-06-19 16:56:57 +010032
SiCongLi1af54162021-10-06 15:25:57 +010033namespace arm_compute
34{
35cl::Image2D create_image2d_from_buffer(const cl::Context &ctx, const cl::Buffer &buffer, const TensorShape &shape2d, DataType data_type, size_t image_row_pitch)
Gian Marco Iodice781cba72020-06-19 16:56:57 +010036{
Gian Marco Iodice6f931342020-09-15 14:17:41 +010037 cl_channel_type cl_data_type;
38
39 switch(data_type)
40 {
41 case DataType::F32:
42 cl_data_type = CL_FLOAT;
43 break;
44 case DataType::F16:
45 cl_data_type = CL_HALF_FLOAT;
46 break;
47 default:
48 ARM_COMPUTE_ERROR("Data type not support with OpenCL image2d");
49 }
50
Gian Marco Iodice781cba72020-06-19 16:56:57 +010051 cl_mem cl_image;
52 cl_int err = CL_SUCCESS;
53
Gian Marco Iodice6f931342020-09-15 14:17:41 +010054 const cl_image_format format = { CL_RGBA, cl_data_type };
Gian Marco Iodice781cba72020-06-19 16:56:57 +010055
56 cl_image_desc desc;
57 memset(&desc, 0, sizeof(desc));
58 desc.image_type = CL_MEM_OBJECT_IMAGE2D;
59 desc.mem_object = buffer();
60 desc.image_row_pitch = image_row_pitch;
61 desc.image_width = shape2d[0];
62 desc.image_height = shape2d[1];
63
64 cl_image = clCreateImage(ctx(), CL_MEM_READ_ONLY, &format, &desc, nullptr, &err);
65
66 ARM_COMPUTE_UNUSED(err);
67 ARM_COMPUTE_ERROR_ON_MSG(err != CL_SUCCESS, "Error during the creation of CL image from buffer");
68
69 return cl::Image2D(cl_image);
70}
SiCongLi1af54162021-10-06 15:25:57 +010071
72namespace experimental
73{
74PostOpCLKernelUtils::PostOpCLKernelUtils(const Config &supported_config)
75 : _supported_config(supported_config)
76{
77 ARM_COMPUTE_ERROR_ON_MSG(supported_config.empty(), "Empty PostOp CL kernel support configuration is not allowed");
78 for(auto it = _supported_config.begin(); it != _supported_config.end(); ++it)
79 {
80 auto post_op_sequence = it->first;
81 auto post_op_slots = std::get<1>(it->second);
82 ARM_COMPUTE_ERROR_ON_MSG(post_op_sequence.size() != post_op_slots.size(), "The number of PostOps must be the same as that of the assigned slots");
83 }
84}
85
86bool PostOpCLKernelUtils::are_post_op_shapes_compliant(const ITensorInfo *dst, const experimental::PostOpList<ITensorInfo *> &post_ops)
87{
SiCongLi1af54162021-10-06 15:25:57 +010088 for(const auto &op : post_ops.get_list())
89 {
90 for(const auto &tensor : op->arguments())
91 {
92 const TensorShape &out_shape = TensorShape::broadcast_shape(dst->tensor_shape(), (*tensor)->tensor_shape());
SiCongLieb8bd812021-10-29 15:05:49 +010093 // All post ops must be elementwise and must not alter the shape of the original dst tensor after broadcasting
SiCongLi1af54162021-10-06 15:25:57 +010094 if(detail::have_different_dimensions(out_shape, dst->tensor_shape(), 0))
95 {
96 return false;
97 }
SiCongLieb8bd812021-10-29 15:05:49 +010098 // NOTE: Kernel limitation: currently only the following broadcasting types are supported:
SiCongLid9287352021-11-03 19:01:22 +000099 // 1. Post op arg is scalar, broadcast in both first and second dims
100 // 2. Post op arg is of shape: second dim=1, first dim=N, broadcast only in second dim
101 // This means this case: Post op arg is of shape: second dim=M, first dim=1, broadcast only in first dim, is NOT supported
SiCongLieb8bd812021-10-29 15:05:49 +0100102 if(dst->dimension(0) > 1 && dst->dimension(1) > 1 && (*tensor)->dimension(0) == 1 && (*tensor)->dimension(1) > 1)
103 {
104 return false;
105 }
SiCongLi1af54162021-10-06 15:25:57 +0100106 }
107 }
108 return true;
109}
110
111bool PostOpCLKernelUtils::is_post_op_sequence_supported(const PostOpList<ITensorInfo *> &post_ops) const
112{
113 if(post_ops.size() == 0)
114 {
115 return true; // Always support cases where no post op is specified
116 }
117 const auto post_op_sequence = get_post_op_sequence(post_ops);
118
119 return _supported_config.find(post_op_sequence) != _supported_config.end();
120}
121
122void PostOpCLKernelUtils::set_post_ops_cl_build_options(CLBuildOptions &build_opts, const PostOpList<ITensorInfo *> &post_ops) const
123{
124 const auto post_op_sequence = get_post_op_sequence(post_ops);
125 const auto slots = std::get<1>(_supported_config.at(post_op_sequence));
126 for(size_t post_op_id = 0; post_op_id < post_ops.size(); ++post_op_id)
127 {
128 const auto &post_op = post_ops.get_list().at(post_op_id);
129 const auto slot_prefix = "-DP" + support::cpp11::to_string(slots[post_op_id]);
130 if(post_op->type() == experimental::PostOpType::Activation)
131 {
132 const auto _post_op = utils::cast::polymorphic_downcast<const experimental::PostOpAct<ITensorInfo *> *>(post_op.get());
133 const auto act_type = slot_prefix + "_ACTIVATION_TYPE=" + lower_string(string_from_activation_func(_post_op->_act_info.activation()));
134 const auto act_a_val = slot_prefix + "_ACTIVATION_A_VAL=" + float_to_string_with_full_precision(_post_op->_act_info.a());
135 const auto act_b_val = slot_prefix + "_ACTIVATION_B_VAL=" + float_to_string_with_full_precision(_post_op->_act_info.b());
136 build_opts.add_option(act_type);
137 build_opts.add_option(act_a_val);
138 build_opts.add_option(act_b_val);
139 }
140 else if(post_op->type() == experimental::PostOpType::Eltwise_Add)
141 {
142 size_t arg_id = 1;
143 const auto eltwise_op = slot_prefix + "_ELTWISE_OP=ADD" + "_X_POS_" + support::cpp11::to_string(post_op->prev_dst_pos());
144 build_opts.add_option(eltwise_op);
145 for(const auto &tensor : post_op->arguments())
146 {
147 const auto height = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_HEIGHT=" + support::cpp11::to_string((*tensor)->dimension(1));
148 const auto width = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_WIDTH=" + support::cpp11::to_string((*tensor)->dimension(0));
149 build_opts.add_option(height);
150 build_opts.add_option(width);
151 ++arg_id;
152 }
153 }
ramelg016049eda2021-10-29 10:52:53 +0100154 else if(post_op->type() == experimental::PostOpType::Eltwise_PRelu)
155 {
156 size_t arg_id = 1;
157 const auto eltwise_op = slot_prefix + "_ELTWISE_OP=PRELU" + "_X_POS_" + support::cpp11::to_string(post_op->prev_dst_pos());
158 build_opts.add_option(eltwise_op);
159 for(const auto &tensor : post_op->arguments())
160 {
161 const auto height = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_HEIGHT=" + support::cpp11::to_string((*tensor)->dimension(1));
162 const auto width = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_WIDTH=" + support::cpp11::to_string((*tensor)->dimension(0));
163 build_opts.add_option(height);
164 build_opts.add_option(width);
165 ++arg_id;
166 }
167 }
SiCongLi1af54162021-10-06 15:25:57 +0100168 }
169}
170
171void PostOpCLKernelUtils::set_post_ops_cl_kernel_name(std::string &kernel_name, const PostOpList<ITensorInfo *> &post_ops) const
172{
173 const auto post_op_sequence = get_post_op_sequence(post_ops);
174 const auto postfix = std::get<0>(_supported_config.at(post_op_sequence));
175 kernel_name += postfix;
176}
177} // namespace experimental
178
179} // namespace arm_compute