| Mike Kelly | 0be3a88 | 2020-01-24 11:27:50 +0000 | [diff] [blame^] | 1 | // |
| 2 | // Copyright © 2020 Arm Ltd. All rights reserved. |
| 3 | // SPDX-License-Identifier: MIT |
| 4 | // |
| 5 | |
| 6 | #include "NeonSpaceToBatchNdWorkload.hpp" |
| 7 | |
| 8 | #include "NeonWorkloadUtils.hpp" |
| 9 | #include <ResolveType.hpp> |
| 10 | |
| 11 | namespace armnn |
| 12 | { |
| 13 | |
| 14 | using namespace armcomputetensorutils; |
| 15 | |
| 16 | arm_compute::Status NeonSpaceToBatchNdWorkloadValidate(const TensorInfo& input, |
| 17 | const TensorInfo& output, |
| 18 | const SpaceToBatchNdDescriptor& descriptor) |
| 19 | { |
| 20 | const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout); |
| 21 | const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout); |
| 22 | |
| 23 | // ArmNN blockShape is [H, W] Cl asks for W, H |
| 24 | int32_t blockHeight = boost::numeric_cast<int32_t>(descriptor.m_BlockShape[0]); |
| 25 | int32_t blockWidth = boost::numeric_cast<int32_t>(descriptor.m_BlockShape[1]); |
| 26 | |
| 27 | arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D( |
| 28 | descriptor.m_PadList[1].first, descriptor.m_PadList[0].first); |
| 29 | arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D( |
| 30 | descriptor.m_PadList[1].second, descriptor.m_PadList[0].second); |
| 31 | |
| 32 | return arm_compute::NESpaceToBatchLayer::validate(&aclInputInfo, |
| 33 | blockWidth, |
| 34 | blockHeight, |
| 35 | paddingLeftTop, |
| 36 | paddingRightBottom, |
| 37 | &aclOutputInfo); |
| 38 | } |
| 39 | |
| 40 | NeonSpaceToBatchNdWorkload::NeonSpaceToBatchNdWorkload(const SpaceToBatchNdQueueDescriptor& desc, |
| 41 | const WorkloadInfo& info) |
| 42 | : BaseWorkload<SpaceToBatchNdQueueDescriptor>(desc, info) |
| 43 | { |
| 44 | m_Data.ValidateInputsOutputs("NESpaceToBatchNdWorkload", 1, 1); |
| 45 | |
| 46 | arm_compute::ITensor& input = |
| 47 | boost::polymorphic_pointer_downcast<IAclTensorHandle>(m_Data.m_Inputs[0])->GetTensor(); |
| 48 | arm_compute::ITensor& output = |
| 49 | boost::polymorphic_pointer_downcast<IAclTensorHandle>(m_Data.m_Outputs[0])->GetTensor(); |
| 50 | |
| 51 | // ArmNN blockShape is [H, W] Cl asks for W, H |
| 52 | int32_t blockHeight = boost::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[0]); |
| 53 | int32_t blockWidth = boost::numeric_cast<int32_t>(m_Data.m_Parameters.m_BlockShape[1]); |
| 54 | |
| 55 | arm_compute::Size2D paddingLeftTop = BuildArmComputeSize2D( |
| 56 | m_Data.m_Parameters.m_PadList[1].first, m_Data.m_Parameters.m_PadList[0].first); |
| 57 | arm_compute::Size2D paddingRightBottom = BuildArmComputeSize2D( |
| 58 | m_Data.m_Parameters.m_PadList[1].second, m_Data.m_Parameters.m_PadList[0].second); |
| 59 | |
| 60 | arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout); |
| 61 | input.info()->set_data_layout(aclDataLayout); |
| 62 | output.info()->set_data_layout(aclDataLayout); |
| 63 | |
| 64 | m_Layer.reset(new arm_compute::NESpaceToBatchLayer()); |
| 65 | m_Layer->configure(&input, |
| 66 | blockWidth, |
| 67 | blockHeight, |
| 68 | paddingLeftTop, |
| 69 | paddingRightBottom, |
| 70 | &output); |
| 71 | m_Layer->prepare(); |
| 72 | } |
| 73 | |
| 74 | void NeonSpaceToBatchNdWorkload::Execute() const |
| 75 | { |
| 76 | if (m_Layer) |
| 77 | { |
| 78 | ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonSpaceToBatchNdWorkload_Execute"); |
| 79 | m_Layer->run(); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | } //namespace armnn |