blob: a7b75309f7b71e1f4c149dbdb7228e8b23397493 [file] [log] [blame]
telsoa014fcda012018-03-09 14:13:49 +00001//
2// Copyright © 2017 Arm Ltd. All rights reserved.
David Beckecb56cd2018-09-05 12:52:57 +01003// SPDX-License-Identifier: MIT
telsoa014fcda012018-03-09 14:13:49 +00004//
5#pragma once
6
7#include <armnn/Tensor.hpp>
8#include <backends/WorkloadInfo.hpp>
9
10namespace armnn
11{
12class ITensorHandle;
13}
14
15template <typename QueueDescriptor>
16void AddInputToWorkload(QueueDescriptor& descriptor,
17 armnn::WorkloadInfo& info,
18 const armnn::TensorInfo& tensorInfo,
19 armnn::ITensorHandle* tensorHandle)
20{
21 descriptor.m_Inputs.push_back(tensorHandle);
22 info.m_InputTensorInfos.push_back(tensorInfo);
23}
24
25template <typename QueueDescriptor>
26void AddOutputToWorkload(QueueDescriptor& descriptor,
27 armnn::WorkloadInfo& info,
28 const armnn::TensorInfo& tensorInfo,
29 armnn::ITensorHandle* tensorHandle)
30{
31 descriptor.m_Outputs.push_back(tensorHandle);
32 info.m_OutputTensorInfos.push_back(tensorInfo);
33}
34
35template <typename QueueDescriptor>
36void SetWorkloadInput(QueueDescriptor& descriptor,
37 armnn::WorkloadInfo& info,
38 unsigned int index,
39 const armnn::TensorInfo& tensorInfo,
40 armnn::ITensorHandle* tensorHandle)
41{
42 descriptor.m_Inputs[index] = tensorHandle;
43 info.m_InputTensorInfos[index] = tensorInfo;
44}
45
46template <typename QueueDescriptor>
47void SetWorkloadOutput(QueueDescriptor& descriptor,
48 armnn::WorkloadInfo& info,
49 unsigned int index,
50 const armnn::TensorInfo& tensorInfo,
51 armnn::ITensorHandle* tensorHandle)
52{
53 descriptor.m_Outputs[index] = tensorHandle;
54 info.m_OutputTensorInfos[index] = tensorInfo;
55}