telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #pragma once |
| 6 | |
| 7 | #include "WorkloadDataFwd.hpp" |
| 8 | |
| 9 | #include "armnn/Types.hpp" |
| 10 | #include "armnn/Tensor.hpp" |
| 11 | #include "armnn/Descriptors.hpp" |
| 12 | #include "armnn/Exceptions.hpp" |
| 13 | #include "InternalTypes.hpp" |
| 14 | #include "OutputHandler.hpp" |
| 15 | #include "CpuTensorHandleFwd.hpp" |
| 16 | |
| 17 | namespace armnn |
| 18 | { |
| 19 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 20 | //A helper function that returns the bias data type required for given input data type. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 21 | DataType GetBiasDataType(DataType inputDataType); |
| 22 | |
| 23 | struct WorkloadInfo; |
| 24 | |
| 25 | struct QueueDescriptor |
| 26 | { |
| 27 | std::vector<ITensorHandle*> m_Inputs; |
| 28 | std::vector<ITensorHandle*> m_Outputs; |
| 29 | |
| 30 | void ValidateInputsOutputs(const std::string& descName, |
| 31 | unsigned int numExpectedIn, unsigned int numExpectedOut) const; |
| 32 | |
| 33 | |
| 34 | protected: |
| 35 | ~QueueDescriptor() = default; |
| 36 | QueueDescriptor() = default; |
| 37 | QueueDescriptor(QueueDescriptor const&) = default; |
| 38 | QueueDescriptor& operator=(QueueDescriptor const&) = default; |
| 39 | }; |
| 40 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 41 | // Base class for queue descriptors which contain parameters. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 42 | template <typename LayerDescriptor> |
| 43 | struct QueueDescriptorWithParameters : public QueueDescriptor |
| 44 | { |
| 45 | LayerDescriptor m_Parameters; |
| 46 | |
| 47 | protected: |
| 48 | ~QueueDescriptorWithParameters() = default; |
| 49 | QueueDescriptorWithParameters() = default; |
| 50 | QueueDescriptorWithParameters(QueueDescriptorWithParameters const&) = default; |
| 51 | QueueDescriptorWithParameters& operator=(QueueDescriptorWithParameters const&) = default; |
| 52 | }; |
| 53 | |
| 54 | struct MemCopyQueueDescriptor : QueueDescriptor |
| 55 | { |
| 56 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 57 | }; |
| 58 | |
| 59 | using InputQueueDescriptor = MemCopyQueueDescriptor; |
| 60 | using OutputQueueDescriptor = MemCopyQueueDescriptor; |
| 61 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 62 | // Softmax layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 63 | struct SoftmaxQueueDescriptor : QueueDescriptorWithParameters<SoftmaxDescriptor> |
| 64 | { |
| 65 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 66 | }; |
| 67 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 68 | // Splitter layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 69 | struct SplitterQueueDescriptor : QueueDescriptorWithParameters<ViewsDescriptor> |
| 70 | { |
| 71 | struct ViewOrigin |
| 72 | { |
| 73 | ViewOrigin() {} |
| 74 | ViewOrigin(std::vector<unsigned int> const& origin) : m_Origin(origin) {} |
| 75 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 76 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 77 | std::vector<unsigned int> m_Origin; |
| 78 | }; |
| 79 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 80 | //View defines a tensor that will be carved from the input tensor. |
| 81 | //View origins are stored here, the extents are defined by sizes of the output tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 82 | std::vector<ViewOrigin> m_ViewOrigins; |
| 83 | |
| 84 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 85 | }; |
| 86 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 87 | // Merger layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 88 | struct MergerQueueDescriptor : QueueDescriptorWithParameters<OriginsDescriptor> |
| 89 | { |
| 90 | struct ViewOrigin |
| 91 | { |
| 92 | ViewOrigin() {} |
| 93 | ViewOrigin(const std::vector<unsigned int>& origin) : m_Origin(origin) {} |
| 94 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 95 | //View origin (size of the vector is the same as number of dimensions of the view). |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 96 | std::vector<unsigned int> m_Origin; |
| 97 | }; |
| 98 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 99 | //View defines a sub-area of the output tensor that will be filled with the corresponding input tensor. |
| 100 | //View origins are stored here, the extents are defined by sizes of the input tensors. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 101 | std::vector<ViewOrigin> m_ViewOrigins; |
| 102 | |
| 103 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 104 | }; |
| 105 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 106 | // Activation layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 107 | struct ActivationQueueDescriptor : QueueDescriptorWithParameters<ActivationDescriptor> |
| 108 | { |
| 109 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 110 | }; |
| 111 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 112 | // Fully connected layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 113 | struct FullyConnectedQueueDescriptor : QueueDescriptorWithParameters<FullyConnectedDescriptor> |
| 114 | { |
| 115 | FullyConnectedQueueDescriptor() |
| 116 | : m_Weight(nullptr) |
| 117 | , m_Bias(nullptr) |
| 118 | { |
| 119 | } |
| 120 | |
| 121 | const ConstCpuTensorHandle* m_Weight; |
| 122 | const ConstCpuTensorHandle* m_Bias; |
| 123 | |
| 124 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 125 | }; |
| 126 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 127 | // Permute layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 128 | struct PermuteQueueDescriptor : QueueDescriptorWithParameters<PermuteDescriptor> |
| 129 | { |
| 130 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 131 | }; |
| 132 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 133 | // Pooling 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 134 | struct Pooling2dQueueDescriptor : QueueDescriptorWithParameters<Pooling2dDescriptor> |
| 135 | { |
| 136 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 137 | }; |
| 138 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 139 | // Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 140 | struct Convolution2dQueueDescriptor : QueueDescriptorWithParameters<Convolution2dDescriptor> |
| 141 | { |
| 142 | Convolution2dQueueDescriptor() |
| 143 | : m_Weight(nullptr) |
| 144 | , m_Bias(nullptr) |
| 145 | { |
| 146 | } |
| 147 | |
| 148 | const ConstCpuTensorHandle* m_Weight; |
| 149 | const ConstCpuTensorHandle* m_Bias; |
| 150 | |
| 151 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 152 | }; |
| 153 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 154 | // Depthwise Convolution 2D layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 155 | struct DepthwiseConvolution2dQueueDescriptor : QueueDescriptorWithParameters<DepthwiseConvolution2dDescriptor> |
| 156 | { |
| 157 | DepthwiseConvolution2dQueueDescriptor() |
| 158 | : m_Weight(nullptr) |
| 159 | , m_Bias(nullptr) |
| 160 | { |
| 161 | } |
| 162 | |
| 163 | const ConstCpuTensorHandle* m_Weight; |
| 164 | const ConstCpuTensorHandle* m_Bias; |
| 165 | |
| 166 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 167 | }; |
| 168 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 169 | // Normalization layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 170 | struct NormalizationQueueDescriptor : QueueDescriptorWithParameters<NormalizationDescriptor> |
| 171 | { |
| 172 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 173 | }; |
| 174 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 175 | // Add layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 176 | struct AdditionQueueDescriptor : QueueDescriptor |
| 177 | { |
| 178 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 179 | }; |
| 180 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 181 | // Multiplication layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 182 | struct MultiplicationQueueDescriptor : QueueDescriptor |
| 183 | { |
| 184 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 185 | }; |
| 186 | |
Francis Murtagh | e7a86a4 | 2018-08-29 12:42:10 +0100 | [diff] [blame] | 187 | // Division layer workload data. |
| 188 | struct DivisionQueueDescriptor : QueueDescriptor |
| 189 | { |
| 190 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 191 | }; |
| 192 | |
David Beck | c2044fe | 2018-09-05 15:00:38 +0100 | [diff] [blame] | 193 | // Subtraction layer workload data. |
| 194 | struct SubtractionQueueDescriptor : QueueDescriptor |
| 195 | { |
| 196 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 197 | }; |
| 198 | |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 199 | // Mean layer workload data. |
narpra01 | 32b9046 | 2018-09-13 11:07:48 +0100 | [diff] [blame] | 200 | struct MeanQueueDescriptor : QueueDescriptorWithParameters<MeanDescriptor> |
narpra01 | a6bf912 | 2018-09-10 09:50:09 +0100 | [diff] [blame] | 201 | { |
| 202 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 203 | }; |
| 204 | |
jimfly01 | 2c9322a | 2018-09-19 10:59:49 +0100 | [diff] [blame] | 205 | // Pad layer workload data |
| 206 | struct PadQueueDescriptor : QueueDescriptorWithParameters<PadDescriptor> |
| 207 | { |
| 208 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 209 | }; |
| 210 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 211 | // Batch norm layer workload data. |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 212 | struct BatchNormalizationQueueDescriptor : QueueDescriptorWithParameters<BatchNormalizationDescriptor> |
| 213 | { |
| 214 | BatchNormalizationQueueDescriptor() |
| 215 | : m_Mean(nullptr) |
| 216 | , m_Variance(nullptr) |
| 217 | , m_Beta(nullptr) |
| 218 | , m_Gamma(nullptr) |
| 219 | { |
| 220 | } |
| 221 | |
| 222 | const ConstCpuTensorHandle* m_Mean; |
| 223 | const ConstCpuTensorHandle* m_Variance; |
| 224 | const ConstCpuTensorHandle* m_Beta; |
| 225 | const ConstCpuTensorHandle* m_Gamma; |
| 226 | |
| 227 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 228 | }; |
| 229 | |
| 230 | struct ResizeBilinearQueueDescriptor : QueueDescriptorWithParameters<ResizeBilinearDescriptor> |
| 231 | { |
| 232 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 233 | }; |
| 234 | |
| 235 | struct FakeQuantizationQueueDescriptor : QueueDescriptorWithParameters<FakeQuantizationDescriptor> |
| 236 | { |
| 237 | FakeQuantizationQueueDescriptor() |
| 238 | : m_Min(nullptr) |
| 239 | , m_Max(nullptr) |
| 240 | { |
| 241 | } |
| 242 | |
| 243 | const ConstCpuTensorHandle* m_Min; |
| 244 | const ConstCpuTensorHandle* m_Max; |
| 245 | |
| 246 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 247 | }; |
| 248 | |
| 249 | struct L2NormalizationQueueDescriptor : QueueDescriptor |
| 250 | { |
| 251 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 252 | }; |
| 253 | |
| 254 | struct ConstantQueueDescriptor : QueueDescriptor |
| 255 | { |
| 256 | ConstantQueueDescriptor() |
| 257 | : m_LayerOutput(nullptr) |
| 258 | { |
| 259 | } |
| 260 | |
| 261 | const ConstCpuTensorHandle* m_LayerOutput; |
| 262 | |
| 263 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 264 | }; |
| 265 | |
| 266 | struct ReshapeQueueDescriptor : QueueDescriptorWithParameters<ReshapeDescriptor> |
| 267 | { |
| 268 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 269 | }; |
| 270 | |
| 271 | struct FloorQueueDescriptor : QueueDescriptor |
| 272 | { |
| 273 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 274 | }; |
| 275 | |
telsoa01 | c577f2c | 2018-08-31 09:22:23 +0100 | [diff] [blame] | 276 | struct LstmQueueDescriptor : QueueDescriptorWithParameters<LstmDescriptor> |
| 277 | { |
| 278 | LstmQueueDescriptor() |
| 279 | : m_InputToInputWeights(nullptr) |
| 280 | , m_InputToForgetWeights(nullptr) |
| 281 | , m_InputToCellWeights(nullptr) |
| 282 | , m_InputToOutputWeights(nullptr) |
| 283 | , m_RecurrentToInputWeights(nullptr) |
| 284 | , m_RecurrentToForgetWeights(nullptr) |
| 285 | , m_RecurrentToCellWeights(nullptr) |
| 286 | , m_RecurrentToOutputWeights(nullptr) |
| 287 | , m_CellToInputWeights(nullptr) |
| 288 | , m_CellToForgetWeights(nullptr) |
| 289 | , m_CellToOutputWeights(nullptr) |
| 290 | , m_InputGateBias(nullptr) |
| 291 | , m_ForgetGateBias(nullptr) |
| 292 | , m_CellBias(nullptr) |
| 293 | , m_OutputGateBias(nullptr) |
| 294 | , m_ProjectionWeights(nullptr) |
| 295 | , m_ProjectionBias(nullptr) |
| 296 | { |
| 297 | } |
| 298 | |
| 299 | const ConstCpuTensorHandle* m_InputToInputWeights; |
| 300 | const ConstCpuTensorHandle* m_InputToForgetWeights; |
| 301 | const ConstCpuTensorHandle* m_InputToCellWeights; |
| 302 | const ConstCpuTensorHandle* m_InputToOutputWeights; |
| 303 | const ConstCpuTensorHandle* m_RecurrentToInputWeights; |
| 304 | const ConstCpuTensorHandle* m_RecurrentToForgetWeights; |
| 305 | const ConstCpuTensorHandle* m_RecurrentToCellWeights; |
| 306 | const ConstCpuTensorHandle* m_RecurrentToOutputWeights; |
| 307 | const ConstCpuTensorHandle* m_CellToInputWeights; |
| 308 | const ConstCpuTensorHandle* m_CellToForgetWeights; |
| 309 | const ConstCpuTensorHandle* m_CellToOutputWeights; |
| 310 | const ConstCpuTensorHandle* m_InputGateBias; |
| 311 | const ConstCpuTensorHandle* m_ForgetGateBias; |
| 312 | const ConstCpuTensorHandle* m_CellBias; |
| 313 | const ConstCpuTensorHandle* m_OutputGateBias; |
| 314 | const ConstCpuTensorHandle* m_ProjectionWeights; |
| 315 | const ConstCpuTensorHandle* m_ProjectionBias; |
| 316 | |
| 317 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 318 | }; |
| 319 | |
| 320 | struct ConvertFp16ToFp32QueueDescriptor : QueueDescriptor |
| 321 | { |
| 322 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 323 | }; |
| 324 | |
| 325 | struct ConvertFp32ToFp16QueueDescriptor : QueueDescriptor |
| 326 | { |
| 327 | void Validate(const WorkloadInfo& workloadInfo) const; |
| 328 | }; |
| 329 | |
telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 330 | } //namespace armnn |