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Sadik Armagan1a9c9f62021-08-05 09:25:15 +0100[diff] [blame^]1/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved.
2///
3/// SPDX-License-Identifier: MIT
4///
5
6namespace armnn
7{
8/**
9@page operator_list Arm NN Operators
10
11@tableofcontents
12
13@section S5_1_operator_list Arm NN Operators
14
15Arm NN supports operators that are listed in below table.
16
17Arm NN supports a wide list of data-types.
18The main data-types that the Machine Learning functions support are the following:
19 <ul>
20 <li><b>BFLOAT16:</b> 16-bit non-standard brain floating point
21 <li><b>QASYMMU8:</b> 8-bit unsigned asymmetric quantized
22 <li><b>QASYMMS8:</b> 8-bit signed asymmetric quantized
23 <li><b>QUANTIZEDSYMM8PERAXIS:</b> 8-bit signed symmetric quantized
24 <li><b>QSYMMS8:</b> 8-bit unsigned symmetric quantized
25 <li><b>QSYMMS16:</b> 16-bit unsigned symmetric quantized
26 <li><b>FLOAT32:</b> 32-bit single precision floating point
27 <li><b>FLOAT16:</b> 16-bit half precision floating point
28 <li><b>SIGNED32:</b> 32-bit signed integer
29 <li><b>BOOLEAN:</b> 8-bit unsigned char
30 <li><b>All:</b> Agnostic to any specific data type
31 </ul>
32
33Arm NN supports the following data layouts (fast changing dimension from right to left):
34 <ul>
35 <li><b>NHWC:</b> Layout where channels are in the fastest changing dimension
36 <li><b>NCHW:</b> Layout where width is in the fastest changing dimension
37 <li><b>All:</b> Agnostic to any specific data layout
38 </ul>
39where N = batches, C = channels, H = height, W = width
40
41<table>
42<caption id="multi_row"></caption>
43<tr>
44 <th>Operator
45 <th>Description
46 <th>Equivalent Android NNAPI Operator
47 <th>Backends
48 <th>Data Layouts
49 <th>Data Types
50<tr>
51 <td rowspan="3">AbsLayer
52 <td rowspan="3"> Layer to perform absolute operation.
53 <td rowspan="3">
54 <ul>
55 <li>ANEURALNETWORKS_ABS
56 </ul>
57 <td>CpuRef
58 <td>
59 <ul>
60 <li>All
61 </ul>
62 <td>
63 <table>
64 <tr><th>
65 <tr><td>BFLOAT16
66 <tr><td>FLOAT16
67 <tr><td>FLOAT32
68 <tr><td>QASYMMS8
69 <tr><td>QASYMMU8
70 <tr><td>QSYMMS16
71 <tr><td>SIGNED32
72 </table>
73<tr>
74 <td>CpuAcc
75 <td>
76 <ul>
77 <li>All
78 </ul>
79 <td>
80 <table>
81 <tr><th>
82 <tr><td>FLOAT16
83 <tr><td>FLOAT32
84 <tr><td>SIGNED32
85 </table>
86<tr>
87 <td>GpuAcc
88 <td>
89 <ul>
90 <li>All
91 </ul>
92 <td>
93 <table>
94 <tr><th>
95 <tr><td>FLOAT16
96 <tr><td>FLOAT32
97 </table>
98<tr>
99 <td rowspan="3">ActivationLayer
100 <td rowspan="3" style="width:200px;"> Layer to simulate an activation layer with the specified activation function.
101 <td rowspan="3">
102 <ul>
103 <li>ANEURALNETWORKS_ABS
104 <li>ANEURALNETWORKS_ELU
105 <li>ANEURALNETWORKS_HARD_SWISH
106 <li>ANEURALNETWORKS_LOGISTIC
107 <li>ANEURALNETWORKS_PRELU
108 <li>ANEURALNETWORKS_RELU
109 <li>ANEURALNETWORKS_RELU1
110 <li>ANEURALNETWORKS_RELU6
111 <li>ANEURALNETWORKS_SQRT
112 <li>ANEURALNETWORKS_TANH
113 </ul>
114 <td>CpuRef
115 <td>
116 <ul>
117 <li>All
118 </ul>
119 <td>
120 <table>
121 <tr><th>
122 <tr><td>BFLOAT16
123 <tr><td>FLOAT16
124 <tr><td>FLOAT32
125 <tr><td>QASYMMS8
126 <tr><td>QASYMMU8
127 <tr><td>QSYMMS16
128 </table>
129<tr>
130 <td>CpuAcc
131 <td>
132 <ul>
133 <li>All
134 </ul>
135 <td>
136 <table>
137 <tr><th>
138 <tr><td>QASYMMU8
139 <tr><td>QASYMMS8
140 <tr><td>QSYMMS16
141 <tr><td>FLOAT16
142 <tr><td>FLOAT32
143 </table>
144<tr>
145 <td>GpuAcc
146 <td>
147 <ul>
148 <li>All
149 </ul>
150 <td>
151 <table>
152 <tr><th>
153 <tr><td>QASYMMU8
154 <tr><td>QASYMMS8
155 <tr><td>QSYMMS16
156 <tr><td>FLOAT16
157 <tr><td>FLOAT32
158 </table>
159<tr>
160 <td rowspan="3">AdditionLayer
161 <td rowspan="3" style="width:200px;"> Layer to add 2 tensors.
162 <td rowspan="3">
163 <ul>
164 <li>ANEURALNETWORKS_ADD
165 </ul>
166 <td>CpuRef
167 <td>
168 <ul>
169 <li>All
170 </ul>
171 <td>
172 <table>
173 <tr><th>
174 <tr><td>BFLOAT16
175 <tr><td>FLOAT16
176 <tr><td>FLOAT32
177 <tr><td>QASYMMS8
178 <tr><td>QASYMMU8
179 <tr><td>QSYMMS16
180 <tr><td>SIGNED32
181 </table>
182<tr>
183 <td>CpuAcc
184 <td>
185 <ul>
186 <li>All
187 </ul>
188 <td>
189 <table>
190 <tr><th>
191 <tr><td>QASYMMU8
192 <tr><td>QASYMMS8
193 <tr><td>QSYMMS16
194 <tr><td>SIGNED32
195 <tr><td>FLOAT16
196 <tr><td>FLOAT32
197 </table>
198<tr>
199 <td>GpuAcc
200 <td>
201 <ul>
202 <li>All
203 </ul>
204 <td>
205 <table>
206 <tr><th>
207 <tr><td>QASYMMU8
208 <tr><td>QASYMMS8
209 <tr><td>QSYMMS16
210 <tr><td>SIGNED32
211 <tr><td>FLOAT16
212 <tr><td>FLOAT32
213 </table>
214<tr>
215 <td rowspan="3">ArgMinMaxLayer
216 <td rowspan="3" style="width:200px;"> Layer to calculate the index of the minimum or maximum values in a tensor
217 based on an axis.
218 <td rowspan="3">
219 <ul>
220 <li>ANEURALNETWORKS_ARGMAX
221 <li>ANEURALNETWORKS_ARGMIN
222 </ul>
223 <td>CpuRef
224 <td>
225 <ul>
226 <li>All
227 </ul>
228 <td>
229 <table>
230 <tr><th>
231 <tr><td>BFLOAT16
232 <tr><td>FLOAT16
233 <tr><td>FLOAT32
234 <tr><td>QASYMMS8
235 <tr><td>QASYMMU8
236 <tr><td>QSYMMS16
237 <tr><td>SIGNED32
238 <tr><td>SIGNED64
239 </table>
240<tr>
241 <td>CpuAcc
242 <td>
243 <ul>
244 <li>All
245 </ul>
246 <td>
247 <table>
248 <tr><th>
249 <tr><td>QASYMMU8
250 <tr><td>QASYMMS8
251 <tr><td>SIGNED32
252 <tr><td>FLOAT16
253 <tr><td>FLOAT32
254 </table>
255<tr>
256 <td>GpuAcc
257 <td>
258 <ul>
259 <li>All
260 </ul>
261 <td>
262 <table>
263 <tr><th>
264 <tr><td>QASYMMU8
265 <tr><td>QASYMMS8
266 <tr><td>SIGNED32
267 <tr><td>FLOAT16
268 <tr><td>FLOAT32
269 </table>
270<tr>
271 <td rowspan="3">BatchNormalizationLayer
272 <td rowspan="3" style="width:200px;"> Layer to perform batch normalization.
273 <td rowspan="3">
274 <ul>
275 <li>N/A
276 </ul>
277 <td>CpuRef
278 <td>
279 <ul>
280 <li>All
281 </ul>
282 <td>
283 <table>
284 <tr><th>
285 <tr><td>BFLOAT16
286 <tr><td>FLOAT16
287 <tr><td>FLOAT32
288 <tr><td>QASYMMS8
289 <tr><td>QASYMMU8
290 <tr><td>QSYMMS16
291 </table>
292<tr>
293 <td>CpuAcc
294 <td>
295 <ul>
296 <li>NHWC
297 <li>NCHW
298 </ul>
299 <td>
300 <table>
301 <tr><th>
302 <tr><td>FLOAT32
303 <tr><td>FLOAT16
304 </table>
305<tr>
306 <td>GpuAcc
307 <td>
308 <ul>
309 <li>NHWC
310 <li>NCHW
311 </ul>
312 <td>
313 <table>
314 <tr><th>
315 <tr><td>FLOAT32
316 <tr><td>FLOAT16
317 </table>
318<tr>
319 <td rowspan="3">BatchToSpaceNdLayer
320 <td rowspan="3" style="width:200px;"> Layer to perform a batch to space transformation.
321 <td rowspan="3">
322 <ul>
323 <li>ANEURALNETWORKS_BATCH_TO_SPACE_ND
324 </ul>
325 <td>CpuRef
326 <td>
327 <ul>
328 <li>All
329 </ul>
330 <td>
331 <table>
332 <tr><th>
333 <tr><td>BFLOAT16
334 <tr><td>FLOAT16
335 <tr><td>FLOAT32
336 <tr><td>QASYMMS8
337 <tr><td>QASYMMU8
338 <tr><td>QSYMMS16
339 </table>
340<tr>
341 <td>CpuAcc
342 <td>
343 <ul>
344 <li>NHWC
345 <li>NCHW
346 </ul>
347 <td>
348 <table>
349 <tr><th>
350 <tr><td>All
351 </table>
352<tr>
353 <td>GpuAcc
354 <td>
355 <ul>
356 <li>NHWC
357 <li>NCHW
358 </ul>
359 <td>
360 <table>
361 <tr><th>
362 <tr><td>All
363 </table>
364<tr>
365 <td rowspan="3">CastLayer
366 <td rowspan="3" style="width:200px;"> Layer to cast a tensor to a type.
367 <td rowspan="3">
368 <ul>
369 <li>ANEURALNETWORKS_CAST
370 </ul>
371 <td>CpuRef
372 <td>
373 <ul>
374 <li>All
375 </ul>
376 <td>
377 <table>
378 <tr><th>
379 <tr><td>BFLOAT16
380 <tr><td>FLOAT16
381 <tr><td>FLOAT32
382 <tr><td>QSYMMS8
383 <tr><td>QASYMMS8
384 <tr><td>QASYMMU8
385 <tr><td>QSYMMS16
386 <tr><td>SIGNED32
387 </table>
388<tr>
389 <td>CpuAcc
390 <td>
391 <ul>
392 <li>All
393 </ul>
394 <td>
395 <table>
396 <tr><th>
397 <tr><td>QASYMMS8
398 <tr><td>QASYMMU8
399 <tr><td>FLOAT16
400 <tr><td>SIGNED32
401 <tr><td>FLOAT32
402 </table>
403<tr>
404 <td>GpuAcc
405 <td>
406 <ul>
407 <li>All
408 </ul>
409 <td>
410 <table>
411 <tr><th>
412 <tr><td>QASYMMS8
413 <tr><td>QASYMMU8
414 <tr><td>SIGNED32
415 <tr><td>FLOAT16
416 <tr><td>FLOAT32
417 </table>
418<tr>
419 <td rowspan="3">ComparisonLayer
420 <td rowspan="3" style="width:200px;"> Layer to compare 2 tensors.
421 <td rowspan="3">
422 <ul>
423 <li>ANEURALNETWORKS_EQUAL
424 <li>ANEURALNETWORKS_GREATER
425 <li>ANEURALNETWORKS_GREATER_EQUAL
426 <li>ANEURALNETWORKS_LESS
427 <li>ANEURALNETWORKS_LESS_EQUAL
428 <li>ANEURALNETWORKS_NOT_EQUAL
429 </ul>
430 <td>CpuRef
431 <td>
432 <ul>
433 <li>All
434 </ul>
435 <td>
436 <table>
437 <tr><th>
438 <tr><td>BFLOAT16
439 <tr><td>FLOAT16
440 <tr><td>FLOAT32
441 <tr><td>BOOLEAN
442 <tr><td>QASYMMS8
443 <tr><td>QASYMMU8
444 <tr><td>QSYMMS16
445 <tr><td>SIGNED32
446 </table>
447<tr>
448 <td>CpuAcc
449 <td>
450 <ul>
451 <li>All
452 </ul>
453 <td>
454 <table>
455 <tr><th>
456 <tr><td>All
457 </table>
458<tr>
459 <td>GpuAcc
460 <td>
461 <ul>
462 <li>All
463 </ul>
464 <td>
465 <table>
466 <tr><th>
467 <tr><td>All
468 </table>
469<tr>
470 <td rowspan="3">ConcatLayer
471 <td rowspan="3" style="width:200px;"> Layer to concatenate tensors along a given axis.
472 <td rowspan="3">
473 <ul>
474 <li>ANEURALNETWORKS_CONCATENATION
475 </ul>
476 <td>CpuRef
477 <td>
478 <ul>
479 <li>All
480 </ul>
481 <td>
482 <table>
483 <tr><th>
484 <tr><td>BFLOAT16
485 <tr><td>FLOAT16
486 <tr><td>FLOAT32
487 <tr><td>QASYMMS8
488 <tr><td>QASYMMU8
489 <tr><td>QSYMMS16
490 </table>
491<tr>
492 <td>CpuAcc
493 <td>
494 <ul>
495 <li>All
496 </ul>
497 <td>
498 <table>
499 <tr><th>
500 <tr><td>QASYMMU8
501 <tr><td>QASYMMS8
502 <tr><td>FLOAT16
503 <tr><td>FLOAT32
504 </table>
505<tr>
506 <td>GpuAcc
507 <td>
508 <ul>
509 <li>All
510 </ul>
511 <td>
512 <table>
513 <tr><th>
514 <tr><td>QASYMMU8
515 <tr><td>QASYMMS8
516 <tr><td>FLOAT16
517 <tr><td>FLOAT32
518 </table>
519<tr>
520 <td rowspan="3">ConstantLayer
521 <td rowspan="3" style="width:200px;"> Layer to provide a constant tensor.
522 <td rowspan="3">
523 <ul>
524 <li>N/A
525 </ul>
526 <td>CpuRef
527 <td>
528 <ul>
529 <li>All
530 </ul>
531 <td>
532 <table>
533 <tr><th>
534 <tr><td>BFLOAT16
535 <tr><td>FLOAT16
536 <tr><td>FLOAT32
537 <tr><td>QASYMMS8
538 <tr><td>QASYMMU8
539 <tr><td>QSYMMS8
540 <tr><td>QSYMMS16
541 <tr><td>SIGNED32
542 </table>
543<tr>
544 <td>CpuAcc
545 <td>
546 <ul>
547 <li>All
548 </ul>
549 <td>
550 <table>
551 <tr><th>
552 <tr><td>All
553 </table>
554<tr>
555 <td>GpuAcc
556 <td>
557 <ul>
558 <li>All
559 </ul>
560 <td>
561 <table>
562 <tr><th>
563 <tr><td>All
564 </table>
565<tr>
566 <td rowspan="3">ConvertBf16ToFp32Layer
567 <td rowspan="3" style="width:200px;"> Layer to convert BFloat16 tensor to Float32 tensor.
568 <td rowspan="3">
569 <ul>
570 <li>N/A
571 </ul>
572 <td>CpuRef
573 <td>
574 <ul>
575 <li>All
576 </ul>
577 <td>
578 <table>
579 <tr><th>
580 <tr><td>BFLOAT16
581 <tr><td>FLOAT32
582 </table>
583<tr>
584 <td>CpuAcc
585 <td>
586 <ul>
587 <li>All
588 </ul>
589 <td>
590 <table>
591 <tr><th>
592 <tr><td>BFLOAT16
593 <tr><td>FLOAT32
594 </table>
595<tr>
596 <td>GpuAcc
597 <td>
598 <ul>
599 <li>All
600 </ul>
601 <td>
602 <table>
603 <tr><th>
604 <tr><td>BFLOAT16
605 <tr><td>FLOAT32
606 </table>
607<tr>
608 <td rowspan="3">ConvertFp16ToFp32Layer
609 <td rowspan="3" style="width:200px;"> Layer to convert Float16 tensor to Float32 tensor.
610 <td rowspan="3">
611 <ul>
612 <li>N/A
613 </ul>
614 <td>CpuRef
615 <td>
616 <ul>
617 <li>All
618 </ul>
619 <td>
620 <table>
621 <tr><th>
622 <tr><td>FLOAT16
623 <tr><td>FLOAT32
624 </table>
625<tr>
626 <td>CpuAcc
627 <td>
628 <ul>
629 <li>All
630 </ul>
631 <td>
632 <table>
633 <tr><th>
634 <tr><td>FLOAT16
635 <tr><td>FLOAT32
636 </table>
637<tr>
638 <td>GpuAcc
639 <td>
640 <ul>
641 <li>All
642 </ul>
643 <td>
644 <table>
645 <tr><th>
646 <tr><td>FLOAT16
647 <tr><td>FLOAT32
648 </table>
649<tr>
650 <td rowspan="3">ConvertFp32ToBf16Layer
651 <td rowspan="3" style="width:200px;"> Layer to convert Float32 tensor to BFloat16 tensor.
652 <td rowspan="3">
653 <ul>
654 <li>N/A
655 </ul>
656 <td>CpuRef
657 <td>
658 <ul>
659 <li>All
660 </ul>
661 <td>
662 <table>
663 <tr><th>
664 <tr><td>BFLOAT16
665 <tr><td>FLOAT32
666 </table>
667<tr>
668 <td>CpuAcc
669 <td>
670 <ul>
671 <li>All
672 </ul>
673 <td>
674 <table>
675 <tr><th>
676 <tr><td>BFLOAT16
677 <tr><td>FLOAT32
678 </table>
679<tr>
680 <td>GpuAcc
681 <td>
682 <ul>
683 <li>All
684 </ul>
685 <td>
686 <table>
687 <tr><th>
688 <tr><td>BFLOAT16
689 <tr><td>FLOAT32
690 </table>
691<tr>
692 <td rowspan="3">ConvertFp32ToFp16Layer
693 <td rowspan="3" style="width:200px;"> Layer to convert Float32 tensor to Float16 tensor.
694 <td rowspan="3">
695 <ul>
696 <li>N/A
697 </ul>
698 <td>CpuRef
699 <td>
700 <ul>
701 <li>All
702 </ul>
703 <td>
704 <table>
705 <tr><th>
706 <tr><td>FLOAT16
707 <tr><td>FLOAT32
708 </table>
709<tr>
710 <td>CpuAcc
711 <td>
712 <ul>
713 <li>All
714 </ul>
715 <td>
716 <table>
717 <tr><th>
718 <tr><td>FLOAT16
719 <tr><td>FLOAT32
720 </table>
721<tr>
722 <td>GpuAcc
723 <td>
724 <ul>
725 <li>All
726 </ul>
727 <td>
728 <table>
729 <tr><th>
730 <tr><td>FLOAT16
731 <tr><td>FLOAT32
732 </table>
733<tr>
734 <td rowspan="3">Convolution2dLayer
735 <td rowspan="3" style="width:200px;"> Layer to compute a convolution operation.
736 <td rowspan="3">
737 <ul>
738 <li>ANEURALNETWORKS_CONV_2D
739 <li>ANEURALNETWORKS_GROUPED_CONV_2D
740 </ul>
741 <td>CpuRef
742 <td>
743 <ul>
744 <li>All
745 </ul>
746 <td>
747 <table>
748 <tr><th>
749 <tr><td>BFLOAT16
750 <tr><td>FLOAT16
751 <tr><td>FLOAT32
752 <tr><td>QASYMMS8
753 <tr><td>QASYMMU8
754 <tr><td>QSYMMS16
755 </table>
756<tr>
757 <td>CpuAcc
758 <td>
759 <ul>
760 <li>NHWC
761 <li>NCHW
762 </ul>
763 <td>
764 <table>
765 <tr><th>
766 <tr><td>SIGNED32
767 <tr><td>FLOAT16
768 <tr><td>FLOAT32
769 <tr><td>QASYMMU8
770 <tr><td>QASYMMS8
771 <tr><td>QUANTIZEDSYMM8PERAXIS
772 </table>
773<tr>
774 <td>GpuAcc
775 <td>
776 <ul>
777 <li>NHWC
778 <li>NCHW
779 </ul>
780 <td>
781 <table>
782 <tr><th>
783 <tr><td>SIGNED32
784 <tr><td>FLOAT16
785 <tr><td>FLOAT32
786 <tr><td>QASYMMU8
787 <tr><td>QASYMMS8
788 <tr><td>QUANTIZEDSYMM8PERAXIS
789 </table>
790<tr>
791 <td rowspan="1">DebugLayer
792 <td rowspan="1" style="width:200px;"> Layer to print out inter layer tensor information.
793 <td rowspan="1">
794 <ul>
795 <li>N/A
796 </ul>
797 <td>CpuRef
798 <td>
799 <ul>
800 <li>All
801 </ul>
802 <td>
803 <table>
804 <tr><th>
805 <tr><td>BFLOAT16
806 <tr><td>FLOAT16
807 <tr><td>FLOAT32
808 <tr><td>QASYMMS8
809 <tr><td>QASYMMU8
810 <tr><td>QSYMMS8
811 <tr><td>QSYMMS16
812 <tr><td>SIGNED32
813 </table>
814<tr>
815 <td rowspan="3">DepthToSpaceLayer
816 <td rowspan="3" style="width:200px;"> Layer to perform Depth to Space transformation.
817 <td rowspan="3">
818 <ul>
819 <li>ANEURALNETWORKS_DEPTH_TO_SPACE
820 </ul>
821 <td>CpuRef
822 <td>
823 <ul>
824 <li>All
825 </ul>
826 <td>
827 <table>
828 <tr><th>
829 <tr><td>BFLOAT16
830 <tr><td>FLOAT16
831 <tr><td>FLOAT32
832 <tr><td>QASYMMS8
833 <tr><td>QASYMMU8
834 <tr><td>QSYMMS16
835 </table>
836<tr>
837 <td>CpuAcc
838 <td>
839 <ul>
840 <li>NHWC
841 <li>NCHW
842 </ul>
843 <td>
844 <table>
845 <tr><th>
846 <tr><td>All
847 </table>
848<tr>
849 <td>GpuAcc
850 <td>
851 <ul>
852 <li>NHWC
853 <li>NCHW
854 </ul>
855 <td>
856 <table>
857 <tr><th>
858 <tr><td>All
859 </table>
860<tr>
861 <td rowspan="3">DepthwiseConvolution2dLayer
862 <td rowspan="3" style="width:200px;"> Layer to compute a deconvolution or transpose convolution.
863 <td rowspan="3">
864 <ul>
865 <li>ANEURALNETWORKS_DEPTHWISE_CONV_2D
866 </ul>
867 <td>CpuRef
868 <td>
869 <ul>
870 <li>All
871 </ul>
872 <td>
873 <table>
874 <tr><th>
875 <tr><td>BFLOAT16
876 <tr><td>FLOAT16
877 <tr><td>FLOAT32
878 <tr><td>QASYMMS8
879 <tr><td>QASYMMU8
880 <tr><td>QSYMMS8
881 <tr><td>QSYMMS16
882 </table>
883<tr>
884 <td>CpuAcc
885 <td>
886 <ul>
887 <li>NHWC
888 <li>NCHW
889 </ul>
890 <td>
891 <table>
892 <tr><th>
893 <tr><td>FLOAT16
894 <tr><td>FLOAT32
895 <tr><td>SIGNED32
896 <tr><td>QASYMMU8
897 <tr><td>QASYMMS8
898 <tr><td>QUANTIZEDSYMM8PERAXIS
899 </table>
900<tr>
901 <td>GpuAcc
902 <td>
903 <ul>
904 <li>NHWC
905 <li>NCHW
906 </ul>
907 <td>
908 <table>
909 <tr><th>
910 <tr><td>FLOAT16
911 <tr><td>FLOAT32
912 <tr><td>SIGNED32
913 <tr><td>QASYMMU8
914 <tr><td>QASYMMS8
915 <tr><td>QUANTIZEDSYMM8PERAXIS
916 </table>
917<tr>
918 <td rowspan="3">DequantizeLayer
919 <td rowspan="3" style="width:200px;"> Layer to dequantize the values in a tensor.
920 <td rowspan="3">
921 <ul>
922 <li>ANEURALNETWORKS_DEQUANTIZE
923 </ul>
924 <td>CpuRef
925 <td>
926 <ul>
927 <li>All
928 </ul>
929 <td>
930 <table>
931 <tr><th>
932 <tr><td>QASYMMS8
933 <tr><td>QASYMMU8
934 <tr><td>QSYMMS8
935 <tr><td>QSYMMS16
936 </table>
937<tr>
938 <td>CpuAcc
939 <td>
940 <ul>
941 <li>All
942 </ul>
943 <td>
944 <table>
945 <tr><th>
946 <tr><td>FLOAT16
947 <tr><td>FLOAT32
948 <tr><td>QASYMMU8
949 <tr><td>QASYMMS8
950 <tr><td>QUANTIZEDSYMM8PERAXIS
951 <tr><td>QSYMMS8
952 <tr><td>QSYMMS16
953 </table>
954<tr>
955 <td>GpuAcc
956 <td>
957 <ul>
958 <li>All
959 </ul>
960 <td>
961 <table>
962 <tr><th>
963 <tr><td>FLOAT16
964 <tr><td>FLOAT32
965 <tr><td>QASYMMU8
966 <tr><td>QASYMMS8
967 <tr><td>QUANTIZEDSYMM8PERAXIS
968 <tr><td>QSYMMS8
969 <tr><td>QSYMMS16
970 </table>
971<tr>
972 <td rowspan="2">DetectionPostProcessLayer
973 <td rowspan="2" style="width:200px;"> Layer to generate the detection output based on center size encoded boxes, class prediction and anchors by doing non maximum suppression (NMS).
974 <td rowspan="2">
975 <ul>
976 <li>ANEURALNETWORKS_DETECTION_POSTPROCESSING
977 </ul>
978 <td>CpuRef
979 <td>
980 <ul>
981 <li>All
982 </ul>
983 <td>
984 <table>
985 <tr><th>
986 <tr><td>BFLOAT16
987 <tr><td>FLOAT16
988 <tr><td>FLOAT32
989 <tr><td>QASYMMS8
990 <tr><td>QASYMMU8
991 <tr><td>QSYMMS16
992 </table>
993<tr>
994 <td>CpuAcc
995 <td>
996 <ul>
997 <li>All
998 </ul>
999 <td>
1000 <table>
1001 <tr><th>
1002 <tr><td>QASYMMU8
1003 <tr><td>QASYMMS8
1004 <tr><td>FLOAT32
1005 </table>
1006<tr>
1007 <td rowspan="3">DivisionLayer
1008 <td rowspan="3" style="width:200px;"> Layer to divide 2 tensors.
1009 <td rowspan="3">
1010 <ul>
1011 <li>ANEURALNETWORKS_DIV
1012 </ul>
1013 <td>CpuRef
1014 <td>
1015 <ul>
1016 <li>All
1017 </ul>
1018 <td>
1019 <table>
1020 <tr><th>
1021 <tr><td>BFLOAT16
1022 <tr><td>FLOAT16
1023 <tr><td>FLOAT32
1024 <tr><td>QASYMMS8
1025 <tr><td>QASYMMU8
1026 <tr><td>QSYMMS16
1027 <tr><td>SIGNED32
1028 </table>
1029<tr>
1030 <td>CpuAcc
1031 <td>
1032 <ul>
1033 <li>All
1034 </ul>
1035 <td>
1036 <table>
1037 <tr><th>
1038 <tr><td>FLOAT16
1039 <tr><td>FLOAT32
1040 </table>
1041<tr>
1042 <td>GpuAcc
1043 <td>
1044 <ul>
1045 <li>All
1046 </ul>
1047 <td>
1048 <table>
1049 <tr><th>
1050 <tr><td>FLOAT16
1051 <tr><td>FLOAT32
1052 </table>
1053<tr>
1054 <td rowspan="3">ElementwiseBaseLayer
1055 <td rowspan="3" style="width:200px;"> Layer to perform Add - Div - Max - Min - Mul operations.
1056 <td rowspan="3">
1057 <ul>
1058 <li>ANEURALNETWORKS_ADD
1059 <li>ANEURALNETWORKS_DIV
1060 <li>ANEURALNETWORKS_MAXIMUM
1061 <li>ANEURALNETWORKS_MINIMUM
1062 <li>ANEURALNETWORKS_MUL
1063 </ul>
1064 <td>CpuRef
1065 <td>
1066 <ul>
1067 <li>All
1068 </ul>
1069 <td>
1070 <table>
1071 <tr><th>
1072 <tr><td>BFLOAT16
1073 <tr><td>FLOAT16
1074 <tr><td>FLOAT32
1075 <tr><td>QASYMMS8
1076 <tr><td>QASYMMU8
1077 <tr><td>QSYMMS16
1078 <tr><td>SIGNED32
1079 </table>
1080<tr>
1081 <td>CpuAcc
1082 <td>
1083 <ul>
1084 <li>All
1085 </ul>
1086 <td>
1087 <table>
1088 <tr><th>
1089 <tr><td>QASYMMU8
1090 <tr><td>QASYMMS8
1091 <tr><td>QSYMMS16
1092 <tr><td>SIGNED32
1093 <tr><td>FLOAT16
1094 <tr><td>FLOAT32
1095 </table>
1096<tr>
1097 <td>GpuAcc
1098 <td>
1099 <ul>
1100 <li>All
1101 </ul>
1102 <td>
1103 <table>
1104 <tr><th>
1105 <tr><td>QASYMMU8
1106 <tr><td>QASYMMS8
1107 <tr><td>QSYMMS16
1108 <tr><td>SIGNED32
1109 <tr><td>FLOAT16
1110 <tr><td>FLOAT32
1111 </table>
1112<tr>
1113 <td rowspan="3">ElementwiseUnaryLayer
1114 <td rowspan="3" style="width:200px;"> Layer to perform Rsqrt - Exp - Neg - Log - Abs - Sin - Sqrt operations.
1115 <td rowspan="3">
1116 <ul>
1117 <li>ANEURALNETWORKS_ABS
1118 <li>ANEURALNETWORKS_EXP
1119 <li>ANEURALNETWORKS_LOG
1120 <li>ANEURALNETWORKS_NEG
1121 <li>ANEURALNETWORKS_RSQRT
1122 <li>ANEURALNETWORKS_SIN
1123 <li>ANEURALNETWORKS_SQRT
1124 </ul>
1125 <td>CpuRef
1126 <td>
1127 <ul>
1128 <li>All
1129 </ul>
1130 <td>
1131 <table>
1132 <tr><th>
1133 <tr><td>BFLOAT16
1134 <tr><td>FLOAT16
1135 <tr><td>FLOAT32
1136 <tr><td>QASYMMS8
1137 <tr><td>QASYMMU8
1138 <tr><td>QSYMMS16
1139 </table>
1140<tr>
1141 <td>CpuAcc
1142 <td>
1143 <ul>
1144 <li>All
1145 </ul>
1146 <td>
1147 <table>
1148 <tr><th>
1149 <tr><td>FLOAT16
1150 <tr><td>FLOAT32
1151 <tr><td>SIGNED32
1152 </table>
1153<tr>
1154 <td>GpuAcc
1155 <td>
1156 <ul>
1157 <li>All
1158 </ul>
1159 <td>
1160 <table>
1161 <tr><th>
1162 <tr><td>FLOAT16
1163 <tr><td>FLOAT32
1164 </table>
1165<tr>
1166 <td rowspan="1">FakeQuantizationLayer
1167 <td rowspan="1" style="width:200px;"> Layer to quantize float values and dequantize afterwards. The current implementation does not dequantize the values.
1168 <td rowspan="1">
1169 <ul>
1170 <li>N/A
1171 </ul>
1172 <td>CpuRef
1173 <td>
1174 <ul>
1175 <li>All
1176 </ul>
1177 <td>
1178 <table>
1179 <tr><th>
1180 <tr><td>FLOAT32
1181 </table>
1182<tr>
1183 <td rowspan="3">FillLayer
1184 <td rowspan="3" style="width:200px;"> Layer to set the values of a tensor with a given value.
1185 <td rowspan="3">
1186 <ul>
1187 <li>ANEURALNETWORKS_FILL
1188 </ul>
1189 <td>CpuRef
1190 <td>
1191 <ul>
1192 <li>All
1193 </ul>
1194 <td>
1195 <table>
1196 <tr><th>
1197 <tr><td>FLOAT16
1198 <tr><td>FLOAT32
1199 <tr><td>SIGNED32
1200 </table>
1201<tr>
1202 <td>CpuAcc
1203 <td>
1204 <ul>
1205 <li>All
1206 </ul>
1207 <td>
1208 <table>
1209 <tr><th>
1210 <tr><td>All
1211 </table>
1212<tr>
1213 <td>GpuAcc
1214 <td>
1215 <ul>
1216 <li>All
1217 </ul>
1218 <td>
1219 <table>
1220 <tr><th>
1221 <tr><td>All
1222 </table>
1223<tr>
1224 <td rowspan="3">FloorLayer
1225 <td rowspan="3" style="width:200px;"> Layer to round the value to the lowest whole number.
1226 <td rowspan="3">
1227 <ul>
1228 <li>ANEURALNETWORKS_FLOOR
1229 </ul>
1230 <td>CpuRef
1231 <td>
1232 <ul>
1233 <li>All
1234 </ul>
1235 <td>
1236 <table>
1237 <tr><th>
1238 <tr><td>BFLOAT16
1239 <tr><td>FLOAT16
1240 <tr><td>FLOAT32
1241 </table>
1242<tr>
1243 <td>CpuAcc
1244 <td>
1245 <ul>
1246 <li>All
1247 </ul>
1248 <td>
1249 <table>
1250 <tr><th>
1251 <tr><td>FLOAT32
1252 <tr><td>FLOAT16
1253 </table>
1254<tr>
1255 <td>GpuAcc
1256 <td>
1257 <ul>
1258 <li>All
1259 </ul>
1260 <td>
1261 <table>
1262 <tr><th>
1263 <tr><td>FLOAT32
1264 <tr><td>FLOAT16
1265 </table>
1266<tr>
1267 <td rowspan="3">FullyConnectedLayer
1268 <td rowspan="3" style="width:200px;"> Layer to perform a fully connected / dense operation.
1269 <td rowspan="3">
1270 <ul>
1271 <li>ANEURALNETWORKS_FULLY_CONNECTED
1272 </ul>
1273 <td>CpuRef
1274 <td>
1275 <ul>
1276 <li>All
1277 </ul>
1278 <td>
1279 <table>
1280 <tr><th>
1281 <tr><td>BFLOAT16
1282 <tr><td>FLOAT16
1283 <tr><td>FLOAT32
1284 <tr><td>QASYMMS8
1285 <tr><td>QASYMMU8
1286 <tr><td>QSYMMS16
1287 </table>
1288<tr>
1289 <td>CpuAcc
1290 <td>
1291 <ul>
1292 <li>NHWC
1293 <li>NCHW
1294 </ul>
1295 <td>
1296 <table>
1297 <tr><th>
1298 <tr><td>SIGNED32
1299 <tr><td>FLOAT16
1300 <tr><td>FLOAT32
1301 <tr><td>QASYMMU8
1302 <tr><td>QASYMMS8
1303 </table>
1304<tr>
1305 <td>GpuAcc
1306 <td>
1307 <ul>
1308 <li>NHWC
1309 <li>NCHW
1310 </ul>
1311 <td>
1312 <table>
1313 <tr><th>
1314 <tr><td>SIGNED32
1315 <tr><td>FLOAT16
1316 <tr><td>FLOAT32
1317 <tr><td>QASYMMU8
1318 <tr><td>QASYMMS8
1319 </table>
1320<tr>
1321 <td rowspan="3">GatherLayer
1322 <td rowspan="3" style="width:200px;"> Layer to perform the gather operation along the chosen axis.
1323 <td rowspan="3">
1324 <ul>
1325 <li>ANEURALNETWORKS_GATHER
1326 </ul>
1327 <td>CpuRef
1328 <td>
1329 <ul>
1330 <li>All
1331 </ul>
1332 <td>
1333 <table>
1334 <tr><th>
1335 <tr><td>BFLOAT16
1336 <tr><td>FLOAT16
1337 <tr><td>FLOAT32
1338 <tr><td>QASYMMS8
1339 <tr><td>QASYMMU8
1340 <tr><td>QSYMMS16
1341 <tr><td>SIGNED32
1342 </table>
1343<tr>
1344 <td>CpuAcc
1345 <td>
1346 <ul>
1347 <li>All
1348 </ul>
1349 <td>
1350 <table>
1351 <tr><th>
1352 <tr><td>All
1353 </table>
1354<tr>
1355 <td>GpuAcc
1356 <td>
1357 <ul>
1358 <li>All
1359 </ul>
1360 <td>
1361 <table>
1362 <tr><th>
1363 <tr><td>All
1364 </table>
1365<tr>
1366 <td rowspan="1">InputLayer
1367 <td rowspan="1" style="width:200px;"> Special layer used to provide input data to the computational network.
1368 <td rowspan="1">
1369 <ul>
1370 <li>N/A
1371 </ul>
1372 <td>All
1373 <td>
1374 <ul>
1375 <li>All
1376 </ul>
1377 <td>
1378 <table>
1379 <tr><th>
1380 <tr><td>All
1381 </table>
1382<tr>
1383 <td rowspan="3">InstanceNormalizationLayer
1384 <td rowspan="3" style="width:200px;"> Layer to perform an instance normalization on a given axis.
1385 <td rowspan="3">
1386 <ul>
1387 <li>ANEURALNETWORKS_INSTANCE_NORMALIZATION
1388 </ul>
1389 <td>CpuRef
1390 <td>
1391 <ul>
1392 <li>All
1393 </ul>
1394 <td>
1395 <table>
1396 <tr><th>
1397 <tr><td>BFLOAT16
1398 <tr><td>FLOAT16
1399 <tr><td>FLOAT32
1400 </table>
1401<tr>
1402 <td>CpuAcc
1403 <td>
1404 <ul>
1405 <li>NHWC
1406 <li>NCHW
1407 </ul>
1408 <td>
1409 <table>
1410 <tr><th>
1411 <tr><td>FLOAT16
1412 <tr><td>FLOAT32
1413 </table>
1414<tr>
1415 <td>GpuAcc
1416 <td>
1417 <ul>
1418 <li>NHWC
1419 <li>NCHW
1420 </ul>
1421 <td>
1422 <table>
1423 <tr><th>
1424 <tr><td>FLOAT16
1425 <tr><td>FLOAT32
1426 </table>
1427<tr>
1428 <td rowspan="3">L2NormalizationLayer
1429 <td rowspan="3" style="width:200px;"> Layer to perform an L2 normalization on a given axis.
1430 <td rowspan="3">
1431 <ul>
1432 <li>ANEURALNETWORKS_L2_NORMALIZATION
1433 </ul>
1434 <td>CpuRef
1435 <td>
1436 <ul>
1437 <li>All
1438 </ul>
1439 <td>
1440 <table>
1441 <tr><th>
1442 <tr><td>BFLOAT16
1443 <tr><td>FLOAT16
1444 <tr><td>FLOAT32
1445 <tr><td>QASYMMS8
1446 <tr><td>QASYMMU8
1447 <tr><td>QSYMMS16
1448 </table>
1449<tr>
1450 <td>CpuAcc
1451 <td>
1452 <ul>
1453 <li>NHWC
1454 <li>NCHW
1455 </ul>
1456 <td>
1457 <table>
1458 <tr><th>
1459 <tr><td>FLOAT16
1460 <tr><td>FLOAT32
1461 </table>
1462<tr>
1463 <td>GpuAcc
1464 <td>
1465 <ul>
1466 <li>NHWC
1467 <li>NCHW
1468 </ul>
1469 <td>
1470 <table>
1471 <tr><th>
1472 <tr><td>FLOAT16
1473 <tr><td>FLOAT32
1474 </table>
1475<tr>
1476 <td rowspan="3">LogSoftmaxLayer
1477 <td rowspan="3" style="width:200px;"> Layer to perform the log softmax activations given logits.
1478 <td rowspan="3">
1479 <ul>
1480 <li>N/A
1481 </ul>
1482 <td>CpuRef
1483 <td>
1484 <ul>
1485 <li>All
1486 </ul>
1487 <td>
1488 <table>
1489 <tr><th>
1490 <tr><td>BFLOAT16
1491 <tr><td>FLOAT16
1492 <tr><td>FLOAT32
1493 </table>
1494<tr>
1495 <td>CpuAcc
1496 <td>
1497 <ul>
1498 <li>All
1499 </ul>
1500 <td>
1501 <table>
1502 <tr><th>
1503 <tr><td>QASYMMU8
1504 <tr><td>QASYMMS8
1505 <tr><td>FLOAT16
1506 <tr><td>FLOAT32
1507 </table>
1508<tr>
1509 <td>GpuAcc
1510 <td>
1511 <ul>
1512 <li>All
1513 </ul>
1514 <td>
1515 <table>
1516 <tr><th>
1517 <tr><td>QASYMMU8
1518 <tr><td>QASYMMS8
1519 <tr><td>FLOAT16
1520 <tr><td>FLOAT32
1521 </table>
1522<tr>
1523 <td rowspan="3">LogicalBinaryLayer
1524 <td rowspan="3" style="width:200px;"> Layer to perform Logical AND - Logical NOT - Logical OR operations.
1525 <td rowspan="3">
1526 <ul>
1527 <li>ANEURALNETWORKS_LOGICAL_AND
1528 <li>ANEURALNETWORKS_LOGICAL_NOT
1529 <li>ANEURALNETWORKS_LOGICAL_OR
1530 </ul>
1531 <td>CpuRef
1532 <td>
1533 <ul>
1534 <li>All
1535 </ul>
1536 <td>
1537 <table>
1538 <tr><th>
1539 <tr><td>BOOLEAN
1540 </table>
1541<tr>
1542 <td>CpuAcc
1543 <td>
1544 <ul>
1545 <li>All
1546 </ul>
1547 <td>
1548 <table>
1549 <tr><th>
1550 <tr><td>BOOLEAN
1551 </table>
1552<tr>
1553 <td>GpuAcc
1554 <td>
1555 <ul>
1556 <li>All
1557 </ul>
1558 <td>
1559 <table>
1560 <tr><th>
1561 <tr><td>BOOLEAN
1562 </table>
1563<tr>
1564 <td rowspan="3">LstmLayer
1565 <td rowspan="3" style="width:200px;"> Layer to perform a single time step in a Long Short-Term Memory (LSTM) operation.
1566 <td rowspan="3">
1567 <ul>
1568 <li>ANEURALNETWORKS_LSTM
1569 </ul>
1570 <td>CpuRef
1571 <td>
1572 <ul>
1573 <li>All
1574 </ul>
1575 <td>
1576 <table>
1577 <tr><th>
1578 <tr><td>BFLOAT16
1579 <tr><td>FLOAT16
1580 <tr><td>QSYMMS16
1581 </table>
1582<tr>
1583 <td>CpuAcc
1584 <td>
1585 <ul>
1586 <li>All
1587 </ul>
1588 <td>
1589 <table>
1590 <tr><th>
1591 <tr><td>FLOAT16
1592 <tr><td>FLOAT32
1593 </table>
1594<tr>
1595 <td>GpuAcc
1596 <td>
1597 <ul>
1598 <li>All
1599 </ul>
1600 <td>
1601 <table>
1602 <tr><th>
1603 <tr><td>FLOAT16
1604 <tr><td>FLOAT32
1605 </table>
1606<tr>
1607 <td rowspan="3">MapLayer
1608 <td rowspan="3" style="width:200px;"> Layer to perform map operation on tensor.
1609 <td rowspan="3">
1610 <ul>
1611 <li>N/A
1612 </ul>
1613 <td>CpuRef
1614 <td>
1615 <ul>
1616 <li>All
1617 </ul>
1618 <td>
1619 <table>
1620 <tr><th>
1621 <tr><td>All
1622 </table>
1623<tr>
1624 <td>CpuAcc
1625 <td>
1626 <ul>
1627 <li>All
1628 </ul>
1629 <td>
1630 <table>
1631 <tr><th>
1632 <tr><td>All
1633 </table>
1634<tr>
1635 <td>GpuAcc
1636 <td>
1637 <ul>
1638 <li>All
1639 </ul>
1640 <td>
1641 <table>
1642 <tr><th>
1643 <tr><td>All
1644 </table>
1645<tr>
1646 <td rowspan="3">MaximumLayer
1647 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise maximum of two tensors.
1648 <td rowspan="3">
1649 <ul>
1650 <li>N/A
1651 </ul>
1652 <td>CpuRef
1653 <td>
1654 <ul>
1655 <li>All
1656 </ul>
1657 <td>
1658 <table>
1659 <tr><th>
1660 <tr><td>BFLOAT16
1661 <tr><td>FLOAT16
1662 <tr><td>FLOAT32
1663 <tr><td>QASYMMS8
1664 <tr><td>QASYMMU8
1665 <tr><td>QSYMMS16
1666 <tr><td>SIGNED32
1667 </table>
1668<tr>
1669 <td>CpuAcc
1670 <td>
1671 <ul>
1672 <li>All
1673 </ul>
1674 <td>
1675 <table>
1676 <tr><th>
1677 <tr><td>QASYMMU8
1678 <tr><td>QASYMMS8
1679 <tr><td>FLOAT16
1680 <tr><td>FLOAT32
1681 <tr><td>SIGNED32
1682 </table>
1683<tr>
1684 <td>GpuAcc
1685 <td>
1686 <ul>
1687 <li>All
1688 </ul>
1689 <td>
1690 <table>
1691 <tr><th>
1692 <tr><td>QASYMMU8
1693 <tr><td>QASYMMS8
1694 <tr><td>QSYMMS16
1695 <tr><td>FLOAT16
1696 <tr><td>FLOAT32
1697 <tr><td>SIGNED32
1698 </table>
1699<tr>
1700 <td rowspan="3">MeanLayer
1701 <td rowspan="3" style="width:200px;"> Layer to perform reduce mean operation.
1702 <td rowspan="3">
1703 <ul>
1704 <li>ANEURALNETWORKS_MEAN
1705 </ul>
1706 <td>CpuRef
1707 <td>
1708 <ul>
1709 <li>All
1710 </ul>
1711 <td>
1712 <table>
1713 <tr><th>
1714 <tr><td>BFLOAT16
1715 <tr><td>FLOAT16
1716 <tr><td>FLOAT32
1717 <tr><td>QASYMMS8
1718 <tr><td>QASYMMU8
1719 <tr><td>QSYMMS16
1720 </table>
1721<tr>
1722 <td>CpuAcc
1723 <td>
1724 <ul>
1725 <li>All
1726 </ul>
1727 <td>
1728 <table>
1729 <tr><th>
1730 <tr><td>QASYMMU8
1731 <tr><td>QASYMMS8
1732 <tr><td>FLOAT16
1733 <tr><td>FLOAT32
1734 </table>
1735<tr>
1736 <td>GpuAcc
1737 <td>
1738 <ul>
1739 <li>All
1740 </ul>
1741 <td>
1742 <table>
1743 <tr><th>
1744 <tr><td>QASYMMU8
1745 <tr><td>QASYMMS8
1746 <tr><td>FLOAT16
1747 <tr><td>FLOAT32
1748 </table>
1749<tr>
1750 <td rowspan="3">MemCopyLayer
1751 <td rowspan="3" style="width:200px;"> Layer to perform memory copy operation.
1752 <td rowspan="3">
1753 <ul>
1754 <li>N/A
1755 </ul>
1756 <td>CpuRef
1757 <td>
1758 <ul>
1759 <li>All
1760 </ul>
1761 <td>
1762 <table>
1763 <tr><th>
1764 <tr><td>BFLOAT16
1765 <tr><td>FLOAT16
1766 <tr><td>FLOAT32
1767 <tr><td>QASYMMS8
1768 <tr><td>QASYMMU8
1769 <tr><td>QSYMMS16
1770 <tr><td>BOOLEAN
1771 </table>
1772<tr>
1773 <td>CpuAcc
1774 <td>
1775 <ul>
1776 <li>All
1777 </ul>
1778 <td>
1779 <table>
1780 <tr><th>
1781 <tr><td>All
1782 </table>
1783<tr>
1784 <td>GpuAcc
1785 <td>
1786 <ul>
1787 <li>All
1788 </ul>
1789 <td>
1790 <table>
1791 <tr><th>
1792 <tr><td>All
1793 </table>
1794<tr>
1795 <td rowspan="3">MemImportLayer
1796 <td rowspan="3" style="width:200px;"> Layer to perform memory import operation.
1797 <td rowspan="3">
1798 <ul>
1799 <li>N/A
1800 </ul>
1801 <td>CpuRef
1802 <td>
1803 <ul>
1804 <li>All
1805 </ul>
1806 <td>
1807 <table>
1808 <tr><th>
1809 <tr><td>All
1810 </table>
1811<tr>
1812 <td>CpuAcc
1813 <td>
1814 <ul>
1815 <li>All
1816 </ul>
1817 <td>
1818 <table>
1819 <tr><th>
1820 <tr><td>All
1821 </table>
1822<tr>
1823 <td>GpuAcc
1824 <td>
1825 <ul>
1826 <li>All
1827 </ul>
1828 <td>
1829 <table>
1830 <tr><th>
1831 <tr><td>All
1832 </table>
1833<tr>
1834 <td rowspan="3">MergeLayer
1835 <td rowspan="3" style="width:200px;"> Layer to concatenate tensors along a given axis.
1836 <td rowspan="3">
1837 <ul>
1838 <li>ANEURALNETWORKS_CONCATENATION
1839 </ul>
1840 <td>CpuRef
1841 <td>
1842 <ul>
1843 <li>All
1844 </ul>
1845 <td>
1846 <table>
1847 <tr><th>
1848 <tr><td>BFLOAT16
1849 <tr><td>FLOAT16
1850 <tr><td>FLOAT32
1851 <tr><td>QASYMMS8
1852 <tr><td>QASYMMU8
1853 <tr><td>QSYMMS16
1854 </table>
1855<tr>
1856 <td>CpuAcc
1857 <td>
1858 <ul>
1859 <li>All
1860 </ul>
1861 <td>
1862 <table>
1863 <tr><th>
1864 <tr><td>QASYMMU8
1865 <tr><td>QASYMMS8
1866 <tr><td>FLOAT16
1867 <tr><td>FLOAT32
1868 </table>
1869<tr>
1870 <td>GpuAcc
1871 <td>
1872 <ul>
1873 <li>All
1874 </ul>
1875 <td>
1876 <table>
1877 <tr><th>
1878 <tr><td>QASYMMU8
1879 <tr><td>QASYMMS8
1880 <tr><td>FLOAT16
1881 <tr><td>FLOAT32
1882 </table>
1883<tr>
1884 <td rowspan="3">MinimumLayer
1885 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise minimum of two tensors.
1886 <td rowspan="3">
1887 <ul>
1888 <li>ANEURALNETWORKS_MINIMUM
1889 </ul>
1890 <td>CpuRef
1891 <td>
1892 <ul>
1893 <li>All
1894 </ul>
1895 <td>
1896 <table>
1897 <tr><th>
1898 <tr><td>BFLOAT16
1899 <tr><td>FLOAT16
1900 <tr><td>FLOAT32
1901 <tr><td>QASYMMS8
1902 <tr><td>QASYMMU8
1903 <tr><td>QSYMMS16
1904 <tr><td>SIGNED32
1905 </table>
1906<tr>
1907 <td>CpuAcc
1908 <td>
1909 <ul>
1910 <li>All
1911 </ul>
1912 <td>
1913 <table>
1914 <tr><th>
1915 <tr><td>QASYMMU8
1916 <tr><td>QASYMMS8
1917 <tr><td>QSYMMS16
1918 <tr><td>FLOAT16
1919 <tr><td>FLOAT32
1920 </table>
1921<tr>
1922 <td>GpuAcc
1923 <td>
1924 <ul>
1925 <li>All
1926 </ul>
1927 <td>
1928 <table>
1929 <tr><th>
1930 <tr><td>QASYMMU8
1931 <tr><td>QASYMMS8
1932 <tr><td>QSYMMS16
1933 <tr><td>FLOAT16
1934 <tr><td>FLOAT32
1935 <tr><td>SIGNED32
1936 </table>
1937<tr>
1938 <td rowspan="3">MultiplicationLayer
1939 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise multiplication of two tensors.
1940 <td rowspan="3">
1941 <ul>
1942 <li>ANEURALNETWORKS_MUL
1943 </ul>
1944 <td>CpuRef
1945 <td>
1946 <ul>
1947 <li>All
1948 </ul>
1949 <td>
1950 <table>
1951 <tr><th>
1952 <tr><td>BFLOAT16
1953 <tr><td>FLOAT16
1954 <tr><td>FLOAT32
1955 <tr><td>QASYMMS8
1956 <tr><td>QASYMMU8
1957 <tr><td>QSYMMS16
1958 <tr><td>SIGNED32
1959 </table>
1960<tr>
1961 <td>CpuAcc
1962 <td>
1963 <ul>
1964 <li>All
1965 </ul>
1966 <td>
1967 <table>
1968 <tr><th>
1969 <tr><td>QASYMMU8
1970 <tr><td>QASYMMS8
1971 <tr><td>QSYMMS16
1972 <tr><td>SIGNED32
1973 <tr><td>FLOAT16
1974 <tr><td>FLOAT32
1975 </table>
1976<tr>
1977 <td>GpuAcc
1978 <td>
1979 <ul>
1980 <li>All
1981 </ul>
1982 <td>
1983 <table>
1984 <tr><th>
1985 <tr><td>QASYMMU8
1986 <tr><td>QASYMMS8
1987 <tr><td>QSYMMS16
1988 <tr><td>SIGNED32
1989 <tr><td>FLOAT16
1990 <tr><td>FLOAT32
1991 <tr><td>SIGNED32
1992 </table>
1993<tr>
1994 <td rowspan="3">NormalizationLayer
1995 <td rowspan="3" style="width:200px;"> Layer to compute normalization operation.
1996 <td rowspan="3">
1997 <ul>
1998 <li>ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION
1999 </ul>
2000 <td>CpuRef
2001 <td>
2002 <ul>
2003 <li>All
2004 </ul>
2005 <td>
2006 <table>
2007 <tr><th>
2008 <tr><td>BFLOAT16
2009 <tr><td>FLOAT16
2010 <tr><td>FLOAT32
2011 <tr><td>QASYMMS8
2012 <tr><td>QASYMMU8
2013 <tr><td>QSYMMS16
2014 </table>
2015<tr>
2016 <td>CpuAcc
2017 <td>
2018 <ul>
2019 <li>NHWC
2020 <li>NCHW
2021 </ul>
2022 <td>
2023 <table>
2024 <tr><th>
2025 <tr><td>FLOAT32
2026 <tr><td>FLOAT16
2027 </table>
2028<tr>
2029 <td>GpuAcc
2030 <td>
2031 <ul>
2032 <li>NHWC
2033 <li>NCHW
2034 </ul>
2035 <td>
2036 <table>
2037 <tr><th>
2038 <tr><td>FLOAT32
2039 <tr><td>FLOAT16
2040 </table>
2041<tr>
2042 <td rowspan="1">OutputLayer
2043 <td rowspan="1" style="width:200px;"> A special layer providing access to a user supplied buffer into which the output of a network can be written.
2044 <td rowspan="1">
2045 <ul>
2046 <li>N/A
2047 </ul>
2048 <td>All
2049 <td>
2050 <ul>
2051 <li>All
2052 </ul>
2053 <td>
2054 <table>
2055 <tr><th>
2056 <tr><td>All
2057 </table>
2058<tr>
2059 <td rowspan="3">PadLayer
2060 <td rowspan="3" style="width:200px;"> Layer to pad a tensor.
2061 <td rowspan="3">
2062 <ul>
2063 <li>ANEURALNETWORKS_PAD
2064 <li>ANEURALNETWORKS_PAD_V2
2065 </ul>
2066 <td>CpuRef
2067 <td>
2068 <ul>
2069 <li>All
2070 </ul>
2071 <td>
2072 <table>
2073 <tr><th>
2074 <tr><td>BFLOAT16
2075 <tr><td>FLOAT16
2076 <tr><td>FLOAT32
2077 <tr><td>QASYMMS8
2078 <tr><td>QASYMMU8
2079 <tr><td>QSYMMS16
2080 </table>
2081<tr>
2082 <td>CpuAcc
2083 <td>
2084 <ul>
2085 <li>NHWC
2086 <li>NCHW
2087 </ul>
2088 <td>
2089 <table>
2090 <tr><th>
2091 <tr><td>All
2092 </table>
2093<tr>
2094 <td>GpuAcc
2095 <td>
2096 <ul>
2097 <li>NHWC
2098 <li>NCHW
2099 </ul>
2100 <td>
2101 <table>
2102 <tr><th>
2103 <tr><td>All
2104 </table>
2105<tr>
2106 <td rowspan="3">PermuteLayer
2107 <td rowspan="3" style="width:200px;"> Layer to transpose an ND tensor.
2108 <td rowspan="3">
2109 <ul>
2110 <li>ANEURALNETWORKS_TRANSPOSE
2111 </ul>
2112 <td>CpuRef
2113 <td>
2114 <ul>
2115 <li>All
2116 </ul>
2117 <td>
2118 <table>
2119 <tr><th>
2120 <tr><td>BFLOAT16
2121 <tr><td>FLOAT16
2122 <tr><td>FLOAT32
2123 <tr><td>QASYMMS8
2124 <tr><td>QASYMMU8
2125 <tr><td>QSYMMS16
2126 </table>
2127<tr>
2128 <td>CpuAcc
2129 <td>
2130 <ul>
2131 <li>NHWC
2132 <li>NCHW
2133 </ul>
2134 <td>
2135 <table>
2136 <tr><th>
2137 <tr><td>All
2138 </table>
2139<tr>
2140 <td>GpuAcc
2141 <td>
2142 <ul>
2143 <li>NHWC
2144 <li>NCHW
2145 </ul>
2146 <td>
2147 <table>
2148 <tr><th>
2149 <tr><td>All
2150 </table>
2151<tr>
2152 <td rowspan="3">Pooling2dLayer
2153 <td rowspan="3" style="width:200px;"> Layer to perform pooling with the specified pooling operation.
2154 <td rowspan="3">
2155 <ul>
2156 <li>ANEURALNETWORKS_AVERAGE_POOL_2D
2157 <li>ANEURALNETWORKS_L2_POOL_2D
2158 <li>ANEURALNETWORKS_MAX_POOL_2D
2159 </ul>
2160 <td>CpuRef
2161 <td>
2162 <ul>
2163 <li>All
2164 </ul>
2165 <td>
2166 <table>
2167 <tr><th>
2168 <tr><td>BFLOAT16
2169 <tr><td>FLOAT16
2170 <tr><td>FLOAT32
2171 <tr><td>QASYMMS8
2172 <tr><td>QASYMMU8
2173 <tr><td>QSYMMS16
2174 </table>
2175<tr>
2176 <td>CpuAcc
2177 <td>
2178 <ul>
2179 <li>NHWC
2180 <li>NCHW
2181 </ul>
2182 <td>
2183 <table>
2184 <tr><th>
2185 <tr><td>QASYMMU8
2186 <tr><td>QASYMMS8
2187 <tr><td>FLOAT16
2188 <tr><td>FLOAT32
2189 </table>
2190<tr>
2191 <td>GpuAcc
2192 <td>
2193 <ul>
2194 <li>NHWC
2195 <li>NCHW
2196 </ul>
2197 <td>
2198 <table>
2199 <tr><th>
2200 <tr><td>QASYMMU8
2201 <tr><td>QASYMMS8
2202 <tr><td>FLOAT16
2203 <tr><td>FLOAT32
2204 </table>
2205<tr>
2206 <td rowspan="1">PreCompiledLayer
2207 <td rowspan="1" style="width:200px;"> Opaque layer provided by a backend which provides an executable representation of a subgraph from the original network.
2208 <td rowspan="1">
2209 <ul>
2210 <li>N/A
2211 </ul>
2212 <td>N/A
2213 <td>N/A
2214 <td>N/A
2215<tr>
2216 <td rowspan="3">PreluLayer
2217 <td rowspan="3" style="width:200px;"> Layer to compute the activation layer with the PRELU activation function.
2218 <td rowspan="3">
2219 <ul>
2220 <li>ANEURALNETWORKS_PRELU
2221 </ul>
2222 <td>CpuRef
2223 <td>
2224 <ul>
2225 <li>All
2226 </ul>
2227 <td>
2228 <table>
2229 <tr><th>
2230 <tr><td>BFLOAT16
2231 <tr><td>FLOAT16
2232 <tr><td>FLOAT32
2233 <tr><td>QASYMMS8
2234 <tr><td>QASYMMU8
2235 <tr><td>QSYMMS16
2236 </table>
2237<tr>
2238 <td>CpuAcc
2239 <td>
2240 <ul>
2241 <li>All
2242 </ul>
2243 <td>
2244 <table>
2245 <tr><th>
2246 <tr><td>QASYMMU8
2247 <tr><td>QASYMMS8
2248 <tr><td>FLOAT16
2249 <tr><td>FLOAT32
2250 </table>
2251<tr>
2252 <td>GpuAcc
2253 <td>
2254 <ul>
2255 <li>All
2256 </ul>
2257 <td>
2258 <table>
2259 <tr><th>
2260 <tr><td>QASYMMU8
2261 <tr><td>QASYMMS8
2262 <tr><td>FLOAT16
2263 <tr><td>FLOAT32
2264 </table>
2265<tr>
2266 <td rowspan="3">QLstmLayer
2267 <td rowspan="3" style="width:200px;"> Layer to perform quantized LSTM (Long Short-Term Memory) operation.
2268 <td rowspan="3">
2269 <ul>
2270 <li>ANEURALNETWORKS_QUANTIZED_LSTM
2271 <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM
2272 </ul>
2273 <td>CpuRef
2274 <td>
2275 <ul>
2276 <li>All
2277 </ul>
2278 <td>
2279 <table>
2280 <tr><th>
2281 <tr><td>All
2282 </table>
2283<tr>
2284 <td>CpuAcc
2285 <td>
2286 <ul>
2287 <li>All
2288 </ul>
2289 <td>
2290 <table>
2291 <tr><th>
2292 <tr><td>QASYMMS8
2293 <tr><td>QASYMMU8
2294 <tr><td>SIGNED32
2295 <tr><td>QSYMMS16
2296 </table>
2297<tr>
2298 <td>GpuAcc
2299 <td>
2300 <ul>
2301 <li>All
2302 </ul>
2303 <td>
2304 <table>
2305 <tr><th>
2306 <tr><td>QASYMMS8
2307 <tr><td>QASYMMU8
2308 <tr><td>SIGNED32
2309 <tr><td>QSYMMS16
2310 </table>
2311<tr>
2312 <td rowspan="3">QuantizeLayer
2313 <td rowspan="3" style="width:200px;"> Layer to perform quantization operation.
2314 <td rowspan="3">
2315 <ul>
2316 <li>ANEURALNETWORKS_QUANTIZE
2317 </ul>
2318 <td>CpuRef
2319 <td>
2320 <ul>
2321 <li>All
2322 </ul>
2323 <td>
2324 <table>
2325 <tr><th>
2326 <tr><td>BFLOAT16
2327 <tr><td>FLOAT16
2328 <tr><td>FLOAT32
2329 <tr><td>QASYMMS8
2330 <tr><td>QASYMMU8
2331 <tr><td>QSYMMS8
2332 <tr><td>QSYMMS16
2333 </table>
2334<tr>
2335 <td>CpuAcc
2336 <td>
2337 <ul>
2338 <li>All
2339 </ul>
2340 <td>
2341 <table>
2342 <tr><th>
2343 <tr><td>QASYMMU8
2344 <tr><td>QASYMMS8
2345 <tr><td>QASYMM16
2346 <tr><td>FLOAT16
2347 <tr><td>FLOAT32
2348 </table>
2349<tr>
2350 <td>GpuAcc
2351 <td>
2352 <ul>
2353 <li>All
2354 </ul>
2355 <td>
2356 <table>
2357 <tr><th>
2358 <tr><td>QASYMMU8
2359 <tr><td>QASYMMS8
2360 <tr><td>QASYMM16
2361 <tr><td>FLOAT16
2362 <tr><td>FLOAT32
2363 </table>
2364<tr>
2365 <td rowspan="3">QuantizedLstmLayer
2366 <td rowspan="3" style="width:200px;"> Layer to perform quantized LSTM (Long Short-Term Memory) operation.
2367 <td rowspan="3">
2368 <ul>
2369 <li>ANEURALNETWORKS_QUANTIZED_LSTM
2370 <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM
2371 </ul>
2372 <td>CpuRef
2373 <td>
2374 <ul>
2375 <li>All
2376 </ul>
2377 <td>
2378 <table>
2379 <tr><th>
2380 <tr><td>All
2381 </table>
2382<tr>
2383 <td>CpuAcc
2384 <td>
2385 <ul>
2386 <li>All
2387 </ul>
2388 <td>
2389 <table>
2390 <tr><th>
2391 <tr><td>SIGNED32
2392 <tr><td>QASYMMU8
2393 <tr><td>QSYMMS16
2394 </table>
2395<tr>
2396 <td>GpuAcc
2397 <td>
2398 <ul>
2399 <li>All
2400 </ul>
2401 <td>
2402 <table>
2403 <tr><th>
2404 <tr><td>SIGNED32
2405 <tr><td>QASYMMU8
2406 <tr><td>QSYMMS16
2407 </table>
2408<tr>
2409 <td rowspan="3">RankLayer
2410 <td rowspan="3" style="width:200px;"> Layer to perform a rank operation.
2411 <td rowspan="3">
2412 <ul>
2413 <li>ANEURALNETWORKS_RANK
2414 </ul>
2415 <td>CpuRef
2416 <td>
2417 <ul>
2418 <li>All
2419 </ul>
2420 <td>
2421 <table>
2422 <tr><th>
2423 <tr><td>All
2424 </table>
2425<tr>
2426 <td>CpuAcc
2427 <td>
2428 <ul>
2429 <li>All
2430 </ul>
2431 <td>
2432 <table>
2433 <tr><th>
2434 <tr><td>All
2435 </table>
2436<tr>
2437 <td>GpuAcc
2438 <td>
2439 <ul>
2440 <li>All
2441 </ul>
2442 <td>
2443 <table>
2444 <tr><th>
2445 <tr><td>All
2446 </table>
2447<tr>
2448 <td rowspan="3">ReduceLayer
2449 <td rowspan="3" style="width:200px;"> Layer to perform reduce with the following operations - ARG_IDX_MAX: Index of the max value - ARG_IDX_MIN: Index of the min value - MEAN_SUM: Mean of sum - PROD: Product - SUM_SQUARE: Sum of squares - SUM: Sum - MIN: Min - MAX: Max
2450 <td rowspan="3">
2451 <ul>
2452 <li>ANEURALNETWORKS_REDUCE_MAX
2453 <li>ANEURALNETWORKS_REDUCE_MIN
2454 <li>ANEURALNETWORKS_REDUCE_SUM
2455 </ul>
2456 <td>CpuRef
2457 <td>
2458 <ul>
2459 <li>All
2460 </ul>
2461 <td>
2462 <table>
2463 <tr><th>
2464 <tr><td>BFLOAT16
2465 <tr><td>FLOAT16
2466 <tr><td>FLOAT32
2467 <tr><td>QASYMMS8
2468 <tr><td>QASYMMU8
2469 <tr><td>QSYMMS16
2470 <tr><td>SIGNED32
2471 </table>
2472<tr>
2473 <td>CpuAcc
2474 <td>
2475 <ul>
2476 <li>All
2477 </ul>
2478 <td>
2479 <table>
2480 <tr><th>
2481 <tr><td>QASYMMU8
2482 <tr><td>QASYMMS8
2483 <tr><td>FLOAT16
2484 <tr><td>FLOAT32
2485 <tr><td>SIGNED32
2486 </table>
2487<tr>
2488 <td>GpuAcc
2489 <td>
2490 <ul>
2491 <li>All
2492 </ul>
2493 <td>
2494 <table>
2495 <tr><th>
2496 <tr><td>QASYMMU8
2497 <tr><td>QASYMMS8
2498 <tr><td>FLOAT16
2499 <tr><td>FLOAT32
2500 <tr><td>SIGNED32
2501 </table>
2502<tr>
2503 <td rowspan="3">ReshapeLayer
2504 <td rowspan="3" style="width:200px;"> Layer to reshape a tensor.
2505 <td rowspan="3">
2506 <ul>
2507 <li>ANEURALNETWORKS_RESHAPE
2508 <li>ANEURALNETWORKS_SQUEEZE
2509 <li>ANEURALNETWORKS_EXPAND_DIMS
2510 </ul>
2511 <td>CpuRef
2512 <td>
2513 <ul>
2514 <li>All
2515 </ul>
2516 <td>
2517 <table>
2518 <tr><th>
2519 <tr><td>BFLOAT16
2520 <tr><td>FLOAT16
2521 <tr><td>FLOAT32
2522 <tr><td>QASYMMS8
2523 <tr><td>QASYMMU8
2524 <tr><td>QSYMMS16
2525 <tr><td>SIGNED32
2526 <tr><td>BOOLEAN
2527 </table>
2528<tr>
2529 <td>CpuAcc
2530 <td>
2531 <ul>
2532 <li>All
2533 </ul>
2534 <td>
2535 <table>
2536 <tr><th>
2537 <tr><td>All
2538 </table>
2539<tr>
2540 <td>GpuAcc
2541 <td>
2542 <ul>
2543 <li>All
2544 </ul>
2545 <td>
2546 <table>
2547 <tr><th>
2548 <tr><td>All
2549 </table>
2550<tr>
2551 <td rowspan="3">ResizeLayer
2552 <td rowspan="3" style="width:200px;"> Layer to perform resize of a tensor using one of the interpolation methods: - Bilinear - Nearest Neighbor.
2553 <td rowspan="3">
2554 <ul>
2555 <li>ANEURALNETWORKS_RESIZE_BILINEAR
2556 <li>ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR
2557 </ul>
2558 <td>CpuRef
2559 <td>
2560 <ul>
2561 <li>All
2562 </ul>
2563 <td>
2564 <table>
2565 <tr><th>
2566 <tr><td>BFLOAT16
2567 <tr><td>FLOAT16
2568 <tr><td>FLOAT32
2569 <tr><td>QASYMMS8
2570 <tr><td>QASYMMU8
2571 <tr><td>QSYMMS16
2572 </table>
2573<tr>
2574 <td>CpuAcc
2575 <td>
2576 <ul>
2577 <li>NHWC
2578 <li>NCHW
2579 </ul>
2580 <td>
2581 <table>
2582 <tr><th>
2583 <tr><td>QASYMMU8
2584 <tr><td>QASYMMS8
2585 <tr><td>FLOAT16
2586 <tr><td>FLOAT32
2587 </table>
2588<tr>
2589 <td>GpuAcc
2590 <td>
2591 <ul>
2592 <li>NHWC
2593 <li>NCHW
2594 </ul>
2595 <td>
2596 <table>
2597 <tr><th>
2598 <tr><td>QASYMMU8
2599 <tr><td>QASYMMS8
2600 <tr><td>FLOAT16
2601 <tr><td>FLOAT32
2602 </table>
2603<tr>
2604 <td rowspan="3">RsqrtLayer
2605 <td rowspan="3" style="width:200px;"> Layer to perform Rsqrt operation.
2606 <td rowspan="3">
2607 <ul>
2608 <li>ANEURALNETWORKS_RSQRT
2609 </ul>
2610 <td>CpuRef
2611 <td>
2612 <ul>
2613 <li>All
2614 </ul>
2615 <td>
2616 <table>
2617 <tr><th>
2618 <tr><td>BFLOAT16
2619 <tr><td>FLOAT16
2620 <tr><td>FLOAT32
2621 <tr><td>QASYMMS8
2622 <tr><td>QASYMMU8
2623 <tr><td>QSYMMS16
2624 <tr><td>SIGNED32
2625 </table>
2626<tr>
2627 <td>CpuAcc
2628 <td>
2629 <ul>
2630 <li>All
2631 </ul>
2632 <td>
2633 <table>
2634 <tr><th>
2635 <tr><td>FLOAT16
2636 <tr><td>FLOAT32
2637 <tr><td>SIGNED32
2638 </table>
2639<tr>
2640 <td>GpuAcc
2641 <td>
2642 <ul>
2643 <li>All
2644 </ul>
2645 <td>
2646 <table>
2647 <tr><th>
2648 <tr><td>FLOAT16
2649 <tr><td>FLOAT32
2650 </table>
2651<tr>
2652 <td rowspan="3">ShapeLayer
2653 <td rowspan="3" style="width:200px;"> Layer to return the shape of the input tensor.
2654 <td rowspan="3">
2655 <ul>
2656 <li>N/A
2657 </ul>
2658 <td>CpuRef
2659 <td>
2660 <ul>
2661 <li>All
2662 </ul>
2663 <td>
2664 <table>
2665 <tr><th>
2666 <tr><td>All
2667 </table>
2668<tr>
2669 <td>CpuAcc
2670 <td>
2671 <ul>
2672 <li>All
2673 </ul>
2674 <td>
2675 <table>
2676 <tr><th>
2677 <tr><td>All
2678 </table>
2679<tr>
2680 <td>GpuAcc
2681 <td>
2682 <ul>
2683 <li>All
2684 </ul>
2685 <td>
2686 <table>
2687 <tr><th>
2688 <tr><td>All
2689 </table>
2690<tr>
2691 <td rowspan="3">SliceLayer
2692 <td rowspan="3" style="width:200px;"> Layer to perform tensor slicing.
2693 <td rowspan="3">
2694 <ul>
2695 <li>ANEURALNETWORKS_SLICE
2696 </ul>
2697 <td>CpuRef
2698 <td>
2699 <ul>
2700 <li>All
2701 </ul>
2702 <td>
2703 <table>
2704 <tr><th>
2705 <tr><td>BFLOAT16
2706 <tr><td>FLOAT32
2707 <tr><td>QASYMMS8
2708 <tr><td>QASYMMU8
2709 <tr><td>QSYMMS16
2710 </table>
2711<tr>
2712 <td>CpuAcc
2713 <td>
2714 <ul>
2715 <li>All
2716 </ul>
2717 <td>
2718 <table>
2719 <tr><th>
2720 <tr><td>All
2721 </table>
2722<tr>
2723 <td>GpuAcc
2724 <td>
2725 <ul>
2726 <li>All
2727 </ul>
2728 <td>
2729 <table>
2730 <tr><th>
2731 <tr><td>All
2732 </table>
2733<tr>
2734 <td rowspan="3">SoftmaxLayer
2735 <td rowspan="3" style="width:200px;"> Layer to perform softmax, log-softmax operation over the specified axis.
2736 <td rowspan="3">
2737 <ul>
2738 <li>ANEURALNETWORKS_LOG_SOFTMAX
2739 <li>ANEURALNETWORKS_SOFTMAX
2740 </ul>
2741 <td>CpuRef
2742 <td>
2743 <ul>
2744 <li>All
2745 </ul>
2746 <td>
2747 <table>
2748 <tr><th>
2749 <tr><td>BFLOAT16
2750 <tr><td>FLOAT16
2751 <tr><td>FLOAT32
2752 <tr><td>QASYMMS8
2753 <tr><td>QASYMMU8
2754 <tr><td>QSYMMS8
2755 <tr><td>QSYMMS16
2756 </table>
2757<tr>
2758 <td>CpuAcc
2759 <td>
2760 <ul>
2761 <li>All
2762 </ul>
2763 <td>
2764 <table>
2765 <tr><th>
2766 <tr><td>QASYMMU8
2767 <tr><td>QASYMMS8
2768 <tr><td>FLOAT16
2769 <tr><td>FLOAT32
2770 </table>
2771<tr>
2772 <td>GpuAcc
2773 <td>
2774 <ul>
2775 <li>All
2776 </ul>
2777 <td>
2778 <table>
2779 <tr><th>
2780 <tr><td>QASYMMU8
2781 <tr><td>QASYMMS8
2782 <tr><td>FLOAT16
2783 <tr><td>FLOAT32
2784 </table>
2785<tr>
2786 <td rowspan="3">SpaceToBatchNdLayer
2787 <td rowspan="3" style="width:200px;"> Layer to divide spatial dimensions of the tensor into a grid of blocks and interleaves these blocks with the batch dimension.
2788 <td rowspan="3">
2789 <ul>
2790 <li>ANEURALNETWORKS_SPACE_TO_BATCH_ND
2791 </ul>
2792 <td>CpuRef
2793 <td>
2794 <ul>
2795 <li>All
2796 </ul>
2797 <td>
2798 <table>
2799 <tr><th>
2800 <tr><td>BFLOAT16
2801 <tr><td>FLOAT16
2802 <tr><td>FLOAT32
2803 <tr><td>QASYMMS8
2804 <tr><td>QASYMMU8
2805 <tr><td>QSYMMS16
2806 </table>
2807<tr>
2808 <td>CpuAcc
2809 <td>
2810 <ul>
2811 <li>NHWC
2812 <li>NCHW
2813 </ul>
2814 <td>
2815 <table>
2816 <tr><th>
2817 <tr><td>All
2818 </table>
2819<tr>
2820 <td>GpuAcc
2821 <td>
2822 <ul>
2823 <li>NHWC
2824 <li>NCHW
2825 </ul>
2826 <td>
2827 <table>
2828 <tr><th>
2829 <tr><td>All
2830 </table>
2831<tr>
2832 <td rowspan="3">SpaceToDepthLayer
2833 <td rowspan="3" style="width:200px;"> Layer to rearrange blocks of spatial data into depth.
2834 <td rowspan="3">
2835 <ul>
2836 <li>ANEURALNETWORKS_SPACE_TO_DEPTH
2837 </ul>
2838 <td>CpuRef
2839 <td>
2840 <ul>
2841 <li>All
2842 </ul>
2843 <td>
2844 <table>
2845 <tr><th>
2846 <tr><td>BFLOAT16
2847 <tr><td>FLOAT16
2848 <tr><td>FLOAT32
2849 <tr><td>QASYMMS8
2850 <tr><td>QASYMMU8
2851 <tr><td>QSYMMS16
2852 </table>
2853<tr>
2854 <td>CpuAcc
2855 <td>
2856 <ul>
2857 <li>NHWC
2858 <li>NCHW
2859 </ul>
2860 <td>
2861 <table>
2862 <tr><th>
2863 <tr><td>All
2864 </table>
2865<tr>
2866 <td>GpuAcc
2867 <td>
2868 <ul>
2869 <li>NHWC
2870 <li>NCHW
2871 </ul>
2872 <td>
2873 <table>
2874 <tr><th>
2875 <tr><td>All
2876 </table>
2877<tr>
2878 <td rowspan="3">SplitterLayer
2879 <td rowspan="3" style="width:200px;"> Layer to split a tensor along a given axis.
2880 <td rowspan="3">
2881 <ul>
2882 <li>ANEURALNETWORKS_SPLIT
2883 </ul>
2884 <td>CpuRef
2885 <td>
2886 <ul>
2887 <li>All
2888 </ul>
2889 <td>
2890 <table>
2891 <tr><th>
2892 <tr><td>BFLOAT16
2893 <tr><td>FLOAT16
2894 <tr><td>FLOAT32
2895 <tr><td>QASYMMS8
2896 <tr><td>QASYMMU8
2897 <tr><td>QSYMMS16
2898 </table>
2899<tr>
2900 <td>CpuAcc
2901 <td>
2902 <ul>
2903 <li>All
2904 </ul>
2905 <td>
2906 <table>
2907 <tr><th>
2908 <tr><td>All
2909 </table>
2910<tr>
2911 <td>GpuAcc
2912 <td>
2913 <ul>
2914 <li>All
2915 </ul>
2916 <td>
2917 <table>
2918 <tr><th>
2919 <tr><td>All
2920 </table>
2921<tr>
2922 <td rowspan="3">StackLayer
2923 <td rowspan="3" style="width:200px;"> Layer to stack tensors along an axis.
2924 <td rowspan="3">
2925 <ul>
2926 <li>N/A
2927 </ul>
2928 <td>CpuRef
2929 <td>
2930 <ul>
2931 <li>All
2932 </ul>
2933 <td>
2934 <table>
2935 <tr><th>
2936 <tr><td>BFLOAT16
2937 <tr><td>FLOAT16
2938 <tr><td>FLOAT32
2939 <tr><td>QASYMMS8
2940 <tr><td>QASYMMU8
2941 <tr><td>QSYMMS16
2942 </table>
2943<tr>
2944 <td>CpuAcc
2945 <td>
2946 <ul>
2947 <li>All
2948 </ul>
2949 <td>
2950 <table>
2951 <tr><th>
2952 <tr><td>All
2953 </table>
2954<tr>
2955 <td>GpuAcc
2956 <td>
2957 <ul>
2958 <li>All
2959 </ul>
2960 <td>
2961 <table>
2962 <tr><th>
2963 <tr><td>All
2964 </table>
2965<tr>
2966 <td rowspan="1">StandInLayer
2967 <td rowspan="1" style="width:200px;"> A layer to represent "unknown" or "unsupported" operations in the input graph. It has a configurable number of input and output slots and an optional name.
2968 <td rowspan="1">
2969 <ul>
2970 <li>N/A
2971 </ul>
2972 <td>N/A
2973 <td>N/A
2974 <td>N/A
2975<tr>
2976 <td rowspan="3">StridedSliceLayer
2977 <td rowspan="3" style="width:200px;"> Layer to extract a strided slice of a tensor.
2978 <td rowspan="3">
2979 <ul>
2980 <li>ANEURALNETWORKS_STRIDED_SLICE
2981 </ul>
2982 <td>CpuRef
2983 <td>
2984 <ul>
2985 <li>All
2986 </ul>
2987 <td>
2988 <table>
2989 <tr><th>
2990 <tr><td>BFLOAT16
2991 <tr><td>FLOAT32
2992 <tr><td>QASYMMS8
2993 <tr><td>QASYMMU8
2994 <tr><td>QSYMMS16
2995 </table>
2996<tr>
2997 <td>CpuAcc
2998 <td>
2999 <ul>
3000 <li>All
3001 </ul>
3002 <td>
3003 <table>
3004 <tr><th>
3005 <tr><td>All
3006 </table>
3007<tr>
3008 <td>GpuAcc
3009 <td>
3010 <ul>
3011 <li>All
3012 </ul>
3013 <td>
3014 <table>
3015 <tr><th>
3016 <tr><td>All
3017 </table>
3018<tr>
3019 <td rowspan="3">SubtractionLayer
3020 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise subtract of 2 tensors.
3021 <td rowspan="3">
3022 <ul>
3023 <li>ANEURALNETWORKS_SUB
3024 </ul>
3025 <td>CpuRef
3026 <td>
3027 <ul>
3028 <li>All
3029 </ul>
3030 <td>
3031 <table>
3032 <tr><th>
3033 <tr><td>BFLOAT16
3034 <tr><td>FLOAT16
3035 <tr><td>FLOAT32
3036 <tr><td>QASYMMS8
3037 <tr><td>QASYMMU8
3038 <tr><td>QSYMMS16
3039 <tr><td>SIGNED32
3040 </table>
3041<tr>
3042 <td>CpuAcc
3043 <td>
3044 <ul>
3045 <li>All
3046 </ul>
3047 <td>
3048 <table>
3049 <tr><th>
3050 <tr><td>QASYMMU8
3051 <tr><td>QASYMMS8
3052 <tr><td>QSYMMS16
3053 <tr><td>SIGNED32
3054 <tr><td>FLOAT16
3055 <tr><td>FLOAT32
3056 </table>
3057<tr>
3058 <td>GpuAcc
3059 <td>
3060 <ul>
3061 <li>All
3062 </ul>
3063 <td>
3064 <table>
3065 <tr><th>
3066 <tr><td>QASYMMU8
3067 <tr><td>QASYMMS8
3068 <tr><td>QSYMMS16
3069 <tr><td>SIGNED32
3070 <tr><td>FLOAT16
3071 <tr><td>FLOAT32
3072 </table>
3073<tr>
3074 <td rowspan="3">TransposeConvolution2dLayer
3075 <td rowspan="3" style="width:200px;"> Layer to perform 2D transpose convolution (deconvolution) operation.
3076 <td rowspan="3">
3077 <ul>
3078 <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D
3079 </ul>
3080 <td>CpuRef
3081 <td>
3082 <ul>
3083 <li>All
3084 </ul>
3085 <td>
3086 <table>
3087 <tr><th>
3088 <tr><td>BFLOAT16
3089 <tr><td>FLOAT16
3090 <tr><td>FLOAT32
3091 <tr><td>QASYMMS8
3092 <tr><td>QASYMMU8
3093 <tr><td>QSYMMS8
3094 <tr><td>QSYMMS16
3095 </table>
3096<tr>
3097 <td>CpuAcc
3098 <td>
3099 <ul>
3100 <li>NHWC
3101 <li>NCHW
3102 </ul>
3103 <td>
3104 <table>
3105 <tr><th>
3106 <tr><td>SIGNED32
3107 <tr><td>FLOAT16
3108 <tr><td>FLOAT32
3109 <tr><td>QASYMMU8
3110 <tr><td>QASYMMS8
3111 <tr><td>QUANTIZEDSYMM8PERAXIS
3112 </table>
3113<tr>
3114 <td>GpuAcc
3115 <td>
3116 <ul>
3117 <li>NHWC
3118 <li>NCHW
3119 </ul>
3120 <td>
3121 <table>
3122 <tr><th>
3123 <tr><td>SIGNED32
3124 <tr><td>FLOAT16
3125 <tr><td>FLOAT32
3126 <tr><td>QASYMMU8
3127 <tr><td>QASYMMS8
3128 <tr><td>QUANTIZEDSYMM8PERAXIS
3129 </table>
3130<tr>
3131 <td rowspan="3">TransposeLayer
3132 <td rowspan="3" style="width:200px;"> Layer to transpose a tensor.
3133 <td rowspan="3">
3134 <ul>
3135 <li>ANEURALNETWORKS_TRANSPOSE
3136 </ul>
3137 <td>CpuRef
3138 <td>
3139 <ul>
3140 <li>All
3141 </ul>
3142 <td>
3143 <table>
3144 <tr><th>
3145 <tr><td>BFLOAT16
3146 <tr><td>FLOAT16
3147 <tr><td>FLOAT32
3148 <tr><td>QASYMMS8
3149 <tr><td>QASYMMU8
3150 <tr><td>QSYMMS16
3151 </table>
3152<tr>
3153 <td>CpuAcc
3154 <td>
3155 <ul>
3156 <li>All
3157 </ul>
3158 <td>
3159 <table>
3160 <tr><th>
3161 <tr><td>All
3162 </table>
3163<tr>
3164 <td>GpuAcc
3165 <td>
3166 <ul>
3167 <li>All
3168 </ul>
3169 <td>
3170 <table>
3171 <tr><th>
3172 <tr><td>All
3173 </table>
3174<tr>
3175 <td rowspan="3">UnidirectionalSquenceLstmLayer
3176 <td rowspan="3" style="width:200px;"> Layer to perform unidirectional LSTM operation.
3177 <td rowspan="3">
3178 <ul>
3179 <li>ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_LSTM
3180 </ul>
3181 <td>CpuRef
3182 <td>
3183 <ul>
3184 <li>All
3185 </ul>
3186 <td>
3187 <table>
3188 <tr><th>
3189 <tr><td>All
3190 </table>
3191<tr>
3192 <td>CpuAcc
3193 <td>
3194 <ul>
3195 <li>NHWC
3196 <li>NCHW
3197 </ul>
3198 <td>
3199 <table>
3200 <tr><th>
3201 <tr><td>SIGNED32
3202 <tr><td>FLOAT16
3203 <tr><td>FLOAT32
3204 <tr><td>QASYMMU8
3205 <tr><td>QASYMMS8
3206 <tr><td>QUANTIZEDSYMM8PERAXIS
3207 </table>
3208<tr>
3209 <td>GpuAcc
3210 <td>
3211 <ul>
3212 <li>NHWC
3213 <li>NCHW
3214 </ul>
3215 <td>
3216 <table>
3217 <tr><th>
3218 <tr><td>SIGNED32
3219 <tr><td>FLOAT16
3220 <tr><td>FLOAT32
3221 <tr><td>QASYMMU8
3222 <tr><td>QASYMMS8
3223 <tr><td>QUANTIZEDSYMM8PERAXIS
3224 </table>
3225<tr>
3226 <td rowspan="3">UnmapLayer
3227 <td rowspan="3" style="width:200px;"> Layer to perform unmap operation on tensor.
3228 <td rowspan="3">
3229 <ul>
3230 <li>N/A
3231 </ul>
3232 <td>CpuRef
3233 <td>
3234 <ul>
3235 <li>All
3236 </ul>
3237 <td>
3238 <table>
3239 <tr><th>
3240 <tr><td>All
3241 </table>
3242<tr>
3243 <td>CpuAcc
3244 <td>
3245 <ul>
3246 <li>NHWC
3247 <li>NCHW
3248 </ul>
3249 <td>
3250 <table>
3251 <tr><th>
3252 <tr><td>All
3253 </table>
3254<tr>
3255 <td>GpuAcc
3256 <td>
3257 <ul>
3258 <li>NHWC
3259 <li>NCHW
3260 </ul>
3261 <td>
3262 <table>
3263 <tr><th>
3264 <tr><td>All
3265 </table>
3266</table>
3267
3268*/
3269} // namespace