| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 1 | // |
| 2 | // Copyright © 2017 Arm Ltd. All rights reserved. |
| David Beck | ecb56cd | 2018-09-05 12:52:57 +0100 | [diff] [blame] | 3 | // SPDX-License-Identifier: MIT |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 4 | // |
| 5 | #pragma once |
| 6 | |
| 7 | #include <armnn/Tensor.hpp> |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 8 | |
| Aron Virginas-Tar | c9cc804 | 2018-11-01 16:15:57 +0000 | [diff] [blame] | 9 | #include <backendsCommon/WorkloadInfo.hpp> |
| 10 | |
| telsoa01 | 4fcda01 | 2018-03-09 14:13:49 +0000 | [diff] [blame] | 11 | namespace armnn |
| 12 | { |
| 13 | class ITensorHandle; |
| 14 | } |
| 15 | |
| 16 | template <typename QueueDescriptor> |
| 17 | void AddInputToWorkload(QueueDescriptor& descriptor, |
| 18 | armnn::WorkloadInfo& info, |
| 19 | const armnn::TensorInfo& tensorInfo, |
| 20 | armnn::ITensorHandle* tensorHandle) |
| 21 | { |
| 22 | descriptor.m_Inputs.push_back(tensorHandle); |
| 23 | info.m_InputTensorInfos.push_back(tensorInfo); |
| 24 | } |
| 25 | |
| 26 | template <typename QueueDescriptor> |
| 27 | void AddOutputToWorkload(QueueDescriptor& descriptor, |
| 28 | armnn::WorkloadInfo& info, |
| 29 | const armnn::TensorInfo& tensorInfo, |
| 30 | armnn::ITensorHandle* tensorHandle) |
| 31 | { |
| 32 | descriptor.m_Outputs.push_back(tensorHandle); |
| 33 | info.m_OutputTensorInfos.push_back(tensorInfo); |
| 34 | } |
| 35 | |
| 36 | template <typename QueueDescriptor> |
| 37 | void SetWorkloadInput(QueueDescriptor& descriptor, |
| 38 | armnn::WorkloadInfo& info, |
| 39 | unsigned int index, |
| 40 | const armnn::TensorInfo& tensorInfo, |
| 41 | armnn::ITensorHandle* tensorHandle) |
| 42 | { |
| 43 | descriptor.m_Inputs[index] = tensorHandle; |
| 44 | info.m_InputTensorInfos[index] = tensorInfo; |
| 45 | } |
| 46 | |
| 47 | template <typename QueueDescriptor> |
| 48 | void SetWorkloadOutput(QueueDescriptor& descriptor, |
| 49 | armnn::WorkloadInfo& info, |
| 50 | unsigned int index, |
| 51 | const armnn::TensorInfo& tensorInfo, |
| 52 | armnn::ITensorHandle* tensorHandle) |
| 53 | { |
| 54 | descriptor.m_Outputs[index] = tensorHandle; |
| 55 | info.m_OutputTensorInfos[index] = tensorInfo; |
| 56 | } |