commit 77514da46b29110b63caa7669fac708d88c394af
author Kristofer Jonsson <kristofer.jonsson@arm.com> Wed Sep 23 08:46:41 2020 +0200
committer Kristofer Jonsson <kristofer.jonsson@arm.com> Wed Sep 23 08:46:41 2020 +0200
tree a8fa54a4097c260647b2b32eb49a9fb3b295d614
parent 2b201c340788ac582cec160b7217c2b5405b04f9

Resetting cached cycle counter

Change-Id: Ia2a0ac76fca0fd12efee305a2ea2ebd5b2055b2d

src/ethosu_pmu.c

diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c
index c9a46b0..986396e 100644
--- a/src/ethosu_pmu.c
+++ b/src/ethosu_pmu.c
@@ -153,8 +153,8 @@
     pmcr.word          = ethosu_drv.dev.pmcr;
     pmcr.cycle_cnt_rst = 1;
     ethosu_write_reg(&ethosu_drv.dev, NPU_REG_PMCR, pmcr.word);
-    ethosu_drv.dev.pmcr        = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
-    ethosu_drv.dev.pmccntr_cfg = 0;
+    ethosu_drv.dev.pmcr    = ethosu_read_reg(&ethosu_drv.dev, NPU_REG_PMCR);
+    ethosu_drv.dev.pmccntr = 0;
 }
 
 void ETHOSU_PMU_EVCNTR_ALL_Reset(void)