[Core Driver] Update and remove pmu "v2"-functions
NPU PMU interface currently have functions that have been stepped
each time a compatibilty breaking changed has been introduced. Old
entrypoints have been redefined with macro to use the latest version
for backwards compatibility. This series of patches will remove any
such functions and macro to unify the interface.
Update: Remove all "_v2"-functions and make the latest version the base
entrypoint
Update: Remove all redefine macros to only allow base entrypoint
Change-Id: Ie125e2428a0336fe797c7455014d269a981f6f92
diff --git a/include/pmu_ethosu.h b/include/pmu_ethosu.h
index a344146..ceefda8 100644
--- a/include/pmu_ethosu.h
+++ b/include/pmu_ethosu.h
@@ -139,48 +139,36 @@
/**
* \brief Enable the PMU
*/
-void ETHOSU_PMU_Enable_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_Enable(void) ETHOSU_PMU_Enable_v2(ðosu_drv)
+void ETHOSU_PMU_Enable(struct ethosu_driver *drv);
/**
* \brief Disable the PMU
*/
-void ETHOSU_PMU_Disable_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_Disable(void) ETHOSU_PMU_Disable_v2(ðosu_drv)
+void ETHOSU_PMU_Disable(struct ethosu_driver *drv);
/**
* \brief Set event to count for PMU eventer counter
* \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure
* \param [in] type Event to count
*/
-void ETHOSU_PMU_Set_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type);
-
-#define ETHOSU_PMU_Set_EVTYPER(num, type) ETHOSU_PMU_Set_EVTYPER_v2(ðosu_drv, num, type)
+void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type);
/**
* \brief Get event to count for PMU eventer counter
* \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure
* \return type Event to count
*/
-enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num);
-
-#define ETHOSU_PMU_Get_EVTYPER(num) ETHOSU_PMU_Get_EVTYPER_v2(ðosu_drv, num)
+enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num);
/**
* \brief Reset cycle counter
*/
-void ETHOSU_PMU_CYCCNT_Reset_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_CYCCNT_Reset(void) ETHOSU_PMU_CYCCNT_Reset_v2(ðosu_drv)
+void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv);
/**
* \brief Reset all event counters
*/
-void ETHOSU_PMU_EVCNTR_ALL_Reset_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_EVCNTR_ALL_Reset(void) ETHOSU_PMU_EVCNTR_ALL_Reset_v2(ðosu_drv)
+void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv);
/**
* \brief Enable counters
@@ -189,9 +177,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)
* - cycle counter (bit 31)
*/
-void ETHOSU_PMU_CNTR_Enable_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_CNTR_Enable(mask) ETHOSU_PMU_CNTR_Enable_v2(ðosu_drv, mask)
+void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Disable counters
@@ -200,9 +186,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)
* - cycle counter (bit 31)
*/
-void ETHOSU_PMU_CNTR_Disable_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_CNTR_Disable(mask) ETHOSU_PMU_CNTR_Disable_v2(ðosu_drv, mask)
+void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Determine counters activation
@@ -214,9 +198,7 @@
* - cycle counter activate (bit 31)
* \note ETHOSU specific. Usage breaks CMSIS complience
*/
-uint32_t ETHOSU_PMU_CNTR_Status_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_CNTR_Status(void) ETHOSU_PMU_CNTR_Status_v2(ðosu_drv)
+uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv);
/**
* \brief Read cycle counter (64 bit)
@@ -227,9 +209,7 @@
* is not greater than the former, it means overflow of LSW without
* incrementing MSW has occurred, in which case the former value is used.
*/
-uint64_t ETHOSU_PMU_Get_CCNTR_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_Get_CCNTR(void) ETHOSU_PMU_Get_CCNTR_v2(ðosu_drv)
+uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv);
/**
* \brief Set cycle counter (64 bit)
@@ -238,18 +218,14 @@
* To work-around raciness, counter is temporary disabled if enabled.
* \note ETHOSU specific. Usage breaks CMSIS complience
*/
-void ETHOSU_PMU_Set_CCNTR_v2(struct ethosu_driver *drv, uint64_t val);
-
-#define ETHOSU_PMU_Set_CCNTR(val) ETHOSU_PMU_Set_CCNTR_v2(ðosu_drv, val)
+void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val);
/**
* \brief Read event counter
* \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS)
* \return Event count
*/
-uint32_t ETHOSU_PMU_Get_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num);
-
-#define ETHOSU_PMU_Get_EVCNTR(num) ETHOSU_PMU_Get_EVCNTR_v2(ðosu_drv, num)
+uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num);
/**
* \brief Set event counter value
@@ -257,9 +233,7 @@
* \param [in] val Conter value
* \note ETHOSU specific. Usage breaks CMSIS complience
*/
-void ETHOSU_PMU_Set_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num, uint32_t val);
-
-#define ETHOSU_PMU_Set_EVCNTR(num, val) ETHOSU_PMU_Set_EVCNTR_v2(ðosu_drv, num, val)
+void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val);
/**
* \brief Read counter overflow status
@@ -267,9 +241,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS))
* - cycle counter (bit 31)
*/
-uint32_t ETHOSU_PMU_Get_CNTR_OVS_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_Get_CNTR_OVS(void) ETHOSU_PMU_Get_CNTR_OVS_v2(ðosu_drv)
+uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv);
/**
* \brief Clear counter overflow status
@@ -278,9 +250,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)
* - cycle counter (bit 31)
*/
-void ETHOSU_PMU_Set_CNTR_OVS_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_Set_CNTR_OVS(mask) ETHOSU_PMU_Set_CNTR_OVS_v2(ðosu_drv, mask)
+void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Enable counter overflow interrupt request
@@ -289,9 +259,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)
* - cycle counter (bit 31)
*/
-void ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_Set_CNTR_IRQ_Enable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(ðosu_drv, mask)
+void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Disable counter overflow interrupt request
@@ -300,9 +268,7 @@
* - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)
* - cycle counter (bit 31)
*/
-void ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_Set_CNTR_IRQ_Disable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(ðosu_drv, mask)
+void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Get counters overflow interrupt request stiinings
@@ -312,9 +278,7 @@
* - cycle counter (bit 31)
* \note ETHOSU specific. Usage breaks CMSIS compliance
*/
-uint32_t ETHOSU_PMU_Get_IRQ_Enable_v2(struct ethosu_driver *drv);
-
-#define ETHOSU_PMU_Get_IRQ_Enable(void) ETHOSU_PMU_Get_IRQ_Enable_v2(ðosu_drv)
+uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv);
/**
* \brief Software increment event counter
@@ -323,29 +287,21 @@
* - cycle counter (bit 31)
* \note Software increment bits for one or more event counters.
*/
-void ETHOSU_PMU_CNTR_Increment_v2(struct ethosu_driver *drv, uint32_t mask);
-
-#define ETHOSU_PMU_CNTR_Increment(mask) ETHOSU_PMU_CNTR_Increment_v2(ðosu_drv, mask)
+void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask);
/**
* \brief Set start event number for the cycle counter
* \param [in] start_event Event to trigger start of the cycle counter
* \note Sets the event number that starts the cycle counter.
*/
-void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event);
-
-#define ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(start_event) \
- ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(ðosu_drv, start_event)
+void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event);
/**
* \brief Set stop event number for the cycle counter
* \param [in] stop_event Event number
* \note Sets the event number that stops the cycle counter.
*/
-void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event);
-
-#define ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(stop_event) \
- ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(ðosu_drv, stop_event)
+void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event);
#ifdef __cplusplus
}
diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c
index a5143e2..a88dfb6 100644
--- a/src/ethosu_pmu.c
+++ b/src/ethosu_pmu.c
@@ -84,7 +84,7 @@
* Functions
*****************************************************************************/
-void ETHOSU_PMU_Enable_v2(struct ethosu_driver *drv)
+void ETHOSU_PMU_Enable(struct ethosu_driver *drv)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
struct pmcr_r pmcr;
@@ -94,7 +94,7 @@
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr);
}
-void ETHOSU_PMU_Disable_v2(struct ethosu_driver *drv)
+void ETHOSU_PMU_Disable(struct ethosu_driver *drv)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
struct pmcr_r pmcr;
@@ -104,7 +104,7 @@
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCR, pmcr.word, &drv->dev.pmcr);
}
-void ETHOSU_PMU_Set_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type)
+void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type)
{
ASSERT(num < ETHOSU_PMU_NCOUNTERS);
uint32_t val = pmu_event_value(type);
@@ -112,7 +112,7 @@
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMEVTYPER(num), val, &drv->dev.pmu_evtypr[num]);
}
-enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num)
+enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num)
{
ASSERT(num < ETHOSU_PMU_NCOUNTERS);
uint32_t val = drv->dev.pmu_evtypr[num];
@@ -121,7 +121,7 @@
return type;
}
-void ETHOSU_PMU_CYCCNT_Reset_v2(struct ethosu_driver *drv)
+void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
struct pmcr_r pmcr;
@@ -132,7 +132,7 @@
drv->dev.pmccntr[1] = 0;
}
-void ETHOSU_PMU_EVCNTR_ALL_Reset_v2(struct ethosu_driver *drv)
+void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
struct pmcr_r pmcr;
@@ -146,25 +146,25 @@
}
}
-void ETHOSU_PMU_CNTR_Enable_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCNTENSET, mask, &drv->dev.pmcnten);
}
-void ETHOSU_PMU_CNTR_Disable_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCNTENCLR, mask, &drv->dev.pmcnten);
}
-uint32_t ETHOSU_PMU_CNTR_Status_v2(struct ethosu_driver *drv)
+uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, drv->dev.pmcnten);
return drv->dev.pmcnten;
}
-uint64_t ETHOSU_PMU_Get_CCNTR_v2(struct ethosu_driver *drv)
+uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv)
{
uint32_t val_lo = ethosu_read_reg(&drv->dev, NPU_REG_PMCCNTR_LO);
uint32_t val_hi = ethosu_read_reg(&drv->dev, NPU_REG_PMCCNTR_HI);
@@ -186,15 +186,15 @@
return val;
}
-void ETHOSU_PMU_Set_CCNTR_v2(struct ethosu_driver *drv, uint64_t val)
+void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val)
{
- uint32_t active = ETHOSU_PMU_CNTR_Status_v2(drv) & ETHOSU_PMU_CCNT_Msk;
+ uint32_t active = ETHOSU_PMU_CNTR_Status(drv) & ETHOSU_PMU_CCNT_Msk;
LOG_DEBUG("%s: val=%llu\n", __FUNCTION__, val);
if (active)
{
- ETHOSU_PMU_CNTR_Disable_v2(drv, ETHOSU_PMU_CCNT_Msk);
+ ETHOSU_PMU_CNTR_Disable(drv, ETHOSU_PMU_CCNT_Msk);
}
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, &drv->dev.pmccntr[0]);
@@ -202,11 +202,11 @@
if (active)
{
- ETHOSU_PMU_CNTR_Enable_v2(drv, ETHOSU_PMU_CCNT_Msk);
+ ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk);
}
}
-uint32_t ETHOSU_PMU_Get_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num)
+uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num)
{
ASSERT(num < ETHOSU_PMU_NCOUNTERS);
uint32_t val = ethosu_read_reg(&drv->dev, NPU_REG_PMEVCNTR(num));
@@ -224,55 +224,55 @@
return val;
}
-void ETHOSU_PMU_Set_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num, uint32_t val)
+void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val)
{
ASSERT(num < ETHOSU_PMU_NCOUNTERS);
LOG_DEBUG("%s: num=%u, val=%u\n", __FUNCTION__, num, val);
ethosu_write_reg(&drv->dev, NPU_REG_PMEVCNTR(num), val);
}
-uint32_t ETHOSU_PMU_Get_CNTR_OVS_v2(struct ethosu_driver *drv)
+uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
return ethosu_read_reg(&drv->dev, NPU_REG_PMOVSSET);
}
-void ETHOSU_PMU_Set_CNTR_OVS_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
ethosu_write_reg(&drv->dev, NPU_REG_PMOVSCLR, mask);
}
-void ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMINTSET, mask, &drv->dev.pmint);
}
-void ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMINTCLR, mask, &drv->dev.pmint);
}
-uint32_t ETHOSU_PMU_Get_IRQ_Enable_v2(struct ethosu_driver *drv)
+uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv)
{
LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, drv->dev.pmint);
return drv->dev.pmint;
}
-void ETHOSU_PMU_CNTR_Increment_v2(struct ethosu_driver *drv, uint32_t mask)
+void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask)
{
LOG_DEBUG("%s:\n", __FUNCTION__);
- uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status_v2(drv);
+ uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(drv);
// Disable counters
- ETHOSU_PMU_CNTR_Disable_v2(drv, mask);
+ ETHOSU_PMU_CNTR_Disable(drv, mask);
// Increment cycle counter
if (mask & ETHOSU_PMU_CCNT_Msk)
{
- uint64_t val = ETHOSU_PMU_Get_CCNTR_v2(drv) + 1;
+ uint64_t val = ETHOSU_PMU_Get_CCNTR(drv) + 1;
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, &drv->dev.pmccntr[0]);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32, &drv->dev.pmccntr[1]);
}
@@ -281,16 +281,16 @@
{
if (mask & (1 << i))
{
- uint32_t val = ETHOSU_PMU_Get_EVCNTR_v2(drv, i);
+ uint32_t val = ETHOSU_PMU_Get_EVCNTR(drv, i);
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMEVCNTR(i), val + 1, &drv->dev.pmu_evcntr[i]);
}
}
// Reenable the active counters
- ETHOSU_PMU_CNTR_Enable_v2(drv, cntrs_active);
+ ETHOSU_PMU_CNTR_Enable(drv, cntrs_active);
}
-void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event)
+void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event)
{
LOG_DEBUG("%s: start_event=%u\n", __FUNCTION__, start_event);
uint32_t val = pmu_event_value(start_event);
@@ -300,7 +300,7 @@
ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMCCNTR_CFG, cfg.word, &drv->dev.pmccntr_cfg);
}
-void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event)
+void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event)
{
LOG_DEBUG("%s: stop_event=%u\n", __FUNCTION__, stop_event);
uint32_t val = pmu_event_value(stop_event);