Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | #include "ethosu_interface.h" |
| 19 | |
| 20 | #include "ethosu_config.h" |
| 21 | #include "ethosu_device.h" |
| 22 | #include "ethosu_log.h" |
| 23 | |
| 24 | #include <assert.h> |
| 25 | #include <inttypes.h> |
| 26 | #include <stdbool.h> |
| 27 | #include <stddef.h> |
| 28 | #include <stdio.h> |
| 29 | #include <stdlib.h> |
| 30 | |
| 31 | #define BASEP_OFFSET 4 |
| 32 | |
| 33 | #ifdef ETHOSU65 |
| 34 | #define ADDRESS_BITS 40 |
| 35 | #else |
| 36 | #define ADDRESS_BITS 32 |
| 37 | #endif |
| 38 | |
| 39 | #define ADDRESS_MASK ((1ull << ADDRESS_BITS) - 1) |
| 40 | |
| 41 | #define NPU_CMD_PWR_CLK_MASK (0xC) |
| 42 | |
| 43 | struct ethosu_device *ethosu_dev_init(const void *base_address, uint32_t secure_enable, uint32_t privilege_enable) |
| 44 | { |
| 45 | struct ethosu_device *dev = malloc(sizeof(struct ethosu_device)); |
| 46 | if (!dev) |
| 47 | { |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 48 | LOG_ERR("Failed to allocate memory for Ethos-U device"); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 49 | return NULL; |
| 50 | } |
| 51 | |
| 52 | dev->reg = (volatile struct NPU_REG *)base_address; |
| 53 | dev->secure = secure_enable; |
| 54 | dev->privileged = privilege_enable; |
| 55 | |
| 56 | // Make sure the NPU is in a known state |
| 57 | if (ethosu_dev_soft_reset(dev) != ETHOSU_SUCCESS) |
| 58 | { |
| 59 | free(dev); |
| 60 | return NULL; |
| 61 | } |
| 62 | |
| 63 | return dev; |
| 64 | } |
| 65 | |
| 66 | void ethosu_dev_deinit(struct ethosu_device *dev) |
| 67 | { |
| 68 | free(dev); |
| 69 | } |
| 70 | |
| 71 | enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev) |
| 72 | { |
| 73 | struct regioncfg_r rcfg = {0}; |
| 74 | struct axi_limit0_r l0 = {0}; |
| 75 | struct axi_limit1_r l1 = {0}; |
| 76 | struct axi_limit2_r l2 = {0}; |
| 77 | struct axi_limit3_r l3 = {0}; |
| 78 | |
| 79 | dev->reg->QCONFIG.word = NPU_QCONFIG; |
| 80 | |
| 81 | rcfg.region0 = NPU_REGIONCFG_0; |
| 82 | rcfg.region1 = NPU_REGIONCFG_1; |
| 83 | rcfg.region2 = NPU_REGIONCFG_2; |
| 84 | rcfg.region3 = NPU_REGIONCFG_3; |
| 85 | rcfg.region4 = NPU_REGIONCFG_4; |
| 86 | rcfg.region5 = NPU_REGIONCFG_5; |
| 87 | rcfg.region6 = NPU_REGIONCFG_6; |
| 88 | rcfg.region7 = NPU_REGIONCFG_7; |
| 89 | dev->reg->REGIONCFG.word = rcfg.word; |
| 90 | |
| 91 | l0.max_beats = AXI_LIMIT0_MAX_BEATS_BYTES; |
| 92 | l0.memtype = AXI_LIMIT0_MEM_TYPE; |
| 93 | l0.max_outstanding_read_m1 = AXI_LIMIT0_MAX_OUTSTANDING_READS - 1; |
| 94 | l0.max_outstanding_write_m1 = AXI_LIMIT0_MAX_OUTSTANDING_WRITES - 1; |
| 95 | |
| 96 | l1.max_beats = AXI_LIMIT1_MAX_BEATS_BYTES; |
| 97 | l1.memtype = AXI_LIMIT1_MEM_TYPE; |
| 98 | l1.max_outstanding_read_m1 = AXI_LIMIT1_MAX_OUTSTANDING_READS - 1; |
| 99 | l1.max_outstanding_write_m1 = AXI_LIMIT1_MAX_OUTSTANDING_WRITES - 1; |
| 100 | |
| 101 | l2.max_beats = AXI_LIMIT2_MAX_BEATS_BYTES; |
| 102 | l2.memtype = AXI_LIMIT2_MEM_TYPE; |
| 103 | l2.max_outstanding_read_m1 = AXI_LIMIT2_MAX_OUTSTANDING_READS - 1; |
| 104 | l2.max_outstanding_write_m1 = AXI_LIMIT2_MAX_OUTSTANDING_WRITES - 1; |
| 105 | |
| 106 | l3.max_beats = AXI_LIMIT3_MAX_BEATS_BYTES; |
| 107 | l3.memtype = AXI_LIMIT3_MEM_TYPE; |
| 108 | l3.max_outstanding_read_m1 = AXI_LIMIT3_MAX_OUTSTANDING_READS - 1; |
| 109 | l3.max_outstanding_write_m1 = AXI_LIMIT3_MAX_OUTSTANDING_WRITES - 1; |
| 110 | |
| 111 | dev->reg->AXI_LIMIT0.word = l0.word; |
| 112 | dev->reg->AXI_LIMIT1.word = l1.word; |
| 113 | dev->reg->AXI_LIMIT2.word = l2.word; |
| 114 | dev->reg->AXI_LIMIT3.word = l3.word; |
| 115 | |
| 116 | return ETHOSU_SUCCESS; |
| 117 | } |
| 118 | |
| 119 | enum ethosu_error_codes ethosu_dev_run_command_stream(struct ethosu_device *dev, |
| 120 | const uint8_t *cmd_stream_ptr, |
| 121 | uint32_t cms_length, |
| 122 | const uint64_t *base_addr, |
| 123 | int num_base_addr) |
| 124 | { |
| 125 | assert(num_base_addr <= NPU_REG_BASEP_ARRLEN); |
| 126 | |
| 127 | struct cmd_r cmd; |
| 128 | uint64_t qbase = (uintptr_t)cmd_stream_ptr + BASE_POINTER_OFFSET; |
| 129 | assert(qbase <= ADDRESS_MASK); |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 130 | LOG_DEBUG("QBASE=0x%016llx, QSIZE=%u, base_pointer_offset=0x%08x", qbase, cms_length, BASE_POINTER_OFFSET); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 131 | |
| 132 | dev->reg->QBASE.word[0] = qbase & 0xffffffff; |
| 133 | #ifdef ETHOSU65 |
| 134 | dev->reg->QBASE.word[1] = qbase >> 32; |
| 135 | #endif |
| 136 | dev->reg->QSIZE.word = cms_length; |
| 137 | |
| 138 | for (int i = 0; i < num_base_addr; i++) |
| 139 | { |
| 140 | uint64_t addr = base_addr[i] + BASE_POINTER_OFFSET; |
| 141 | assert(addr <= ADDRESS_MASK); |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 142 | LOG_DEBUG("BASEP%d=0x%016llx", i, addr); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 143 | dev->reg->BASEP[i].word[0] = addr & 0xffffffff; |
| 144 | #ifdef ETHOSU65 |
| 145 | dev->reg->BASEP[i].word[1] = addr >> 32; |
| 146 | #endif |
| 147 | } |
| 148 | |
| 149 | cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; |
| 150 | cmd.transition_to_running_state = 1; |
| 151 | |
| 152 | dev->reg->CMD.word = cmd.word; |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 153 | LOG_DEBUG("CMD=0x%08x", cmd.word); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 154 | |
| 155 | return ETHOSU_SUCCESS; |
| 156 | } |
| 157 | |
| 158 | bool ethosu_dev_handle_interrupt(struct ethosu_device *dev) |
| 159 | { |
| 160 | struct cmd_r cmd; |
| 161 | |
| 162 | // Clear interrupt |
| 163 | cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; |
| 164 | cmd.clear_irq = 1; |
| 165 | dev->reg->CMD.word = cmd.word; |
| 166 | |
| 167 | // If a fault has occured, the NPU needs to be reset |
| 168 | if (dev->reg->STATUS.bus_status || dev->reg->STATUS.cmd_parse_error || dev->reg->STATUS.wd_fault || |
| 169 | dev->reg->STATUS.ecc_fault) |
| 170 | { |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 171 | LOG_DEBUG("NPU fault. status=0x%08x, qread=%" PRIu32, dev->reg->STATUS.word, dev->reg->QREAD.word); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 172 | ethosu_dev_soft_reset(dev); |
| 173 | ethosu_dev_set_clock_and_power(dev, ETHOSU_CLOCK_Q_UNCHANGED, ETHOSU_POWER_Q_DISABLE); |
| 174 | return false; |
| 175 | } |
| 176 | |
| 177 | // Verify that the cmd stream finished executing |
| 178 | return dev->reg->STATUS.cmd_end_reached ? true : false; |
| 179 | } |
| 180 | |
| 181 | bool ethosu_dev_verify_access_state(struct ethosu_device *dev) |
| 182 | { |
| 183 | if (dev->reg->PROT.active_CSL != (dev->secure ? SECURITY_LEVEL_SECURE : SECURITY_LEVEL_NON_SECURE) || |
| 184 | dev->reg->PROT.active_CPL != (dev->privileged ? PRIVILEGE_LEVEL_PRIVILEGED : PRIVILEGE_LEVEL_USER)) |
| 185 | { |
| 186 | return false; |
| 187 | } |
| 188 | return true; |
| 189 | } |
| 190 | |
| 191 | enum ethosu_error_codes ethosu_dev_soft_reset(struct ethosu_device *dev) |
| 192 | { |
| 193 | struct reset_r reset; |
| 194 | |
| 195 | reset.word = 0; |
| 196 | reset.pending_CPL = dev->privileged ? PRIVILEGE_LEVEL_PRIVILEGED : PRIVILEGE_LEVEL_USER; |
| 197 | reset.pending_CSL = dev->secure ? SECURITY_LEVEL_SECURE : SECURITY_LEVEL_NON_SECURE; |
| 198 | |
| 199 | // Reset and set security level |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 200 | LOG_INFO("Soft reset NPU"); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 201 | dev->reg->RESET.word = reset.word; |
| 202 | |
| 203 | // Wait until reset status indicates that reset has been completed |
| 204 | for (int i = 0; i < 100000 && dev->reg->STATUS.reset_status != 0; i++) |
| 205 | { |
| 206 | } |
| 207 | |
| 208 | if (dev->reg->STATUS.reset_status != 0) |
| 209 | { |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 210 | LOG_ERR("Soft reset timed out"); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 211 | return ETHOSU_GENERIC_FAILURE; |
| 212 | } |
| 213 | |
| 214 | // Verify that NPU has switched security state and privilege level |
| 215 | if (ethosu_dev_verify_access_state(dev) != true) |
| 216 | { |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 217 | LOG_ERR("Failed to switch security state and privilege level"); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 218 | return ETHOSU_GENERIC_FAILURE; |
| 219 | } |
| 220 | |
| 221 | // Reinitialize AXI settings |
| 222 | ethosu_dev_axi_init(dev); |
| 223 | |
| 224 | return ETHOSU_SUCCESS; |
| 225 | } |
| 226 | |
| 227 | void ethosu_dev_get_hw_info(struct ethosu_device *dev, struct ethosu_hw_info *hwinfo) |
| 228 | { |
| 229 | struct config_r cfg; |
| 230 | struct id_r id; |
| 231 | |
| 232 | cfg.word = dev->reg->CONFIG.word; |
| 233 | id.word = dev->reg->ID.word; |
| 234 | |
| 235 | hwinfo->cfg.cmd_stream_version = cfg.cmd_stream_version; |
| 236 | hwinfo->cfg.custom_dma = cfg.custom_dma; |
| 237 | hwinfo->cfg.macs_per_cc = cfg.macs_per_cc; |
| 238 | |
| 239 | hwinfo->version.arch_major_rev = id.arch_major_rev; |
| 240 | hwinfo->version.arch_minor_rev = id.arch_minor_rev; |
| 241 | hwinfo->version.arch_patch_rev = id.arch_patch_rev; |
| 242 | hwinfo->version.product_major = id.product_major; |
| 243 | hwinfo->version.version_major = id.version_major; |
| 244 | hwinfo->version.version_minor = id.version_minor; |
| 245 | hwinfo->version.version_status = id.version_status; |
| 246 | } |
| 247 | |
| 248 | enum ethosu_error_codes ethosu_dev_set_clock_and_power(struct ethosu_device *dev, |
| 249 | enum ethosu_clock_q_request clock_q, |
| 250 | enum ethosu_power_q_request power_q) |
| 251 | { |
| 252 | struct cmd_r cmd = {0}; |
| 253 | cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; |
| 254 | |
| 255 | if (power_q != ETHOSU_POWER_Q_UNCHANGED) |
| 256 | { |
| 257 | cmd.power_q_enable = power_q == ETHOSU_POWER_Q_ENABLE ? 1 : 0; |
| 258 | } |
| 259 | if (clock_q != ETHOSU_CLOCK_Q_UNCHANGED) |
| 260 | { |
| 261 | cmd.clock_q_enable = clock_q == ETHOSU_CLOCK_Q_ENABLE ? 1 : 0; |
| 262 | } |
| 263 | |
| 264 | dev->reg->CMD.word = cmd.word; |
Kristofer Jonsson | 089a347 | 2021-11-12 12:52:07 +0100 | [diff] [blame] | 265 | LOG_DEBUG("CMD=0x%08x", cmd.word); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 266 | |
| 267 | return ETHOSU_SUCCESS; |
| 268 | } |
| 269 | |
| 270 | bool ethosu_dev_verify_optimizer_config(struct ethosu_device *dev, uint32_t cfg_in, uint32_t id_in) |
| 271 | { |
| 272 | struct config_r *opt_cfg = (struct config_r *)&cfg_in; |
| 273 | struct config_r hw_cfg; |
| 274 | struct id_r *opt_id = (struct id_r *)&id_in; |
| 275 | struct id_r hw_id; |
| 276 | bool ret = true; |
| 277 | |
| 278 | hw_cfg.word = dev->reg->CONFIG.word; |
| 279 | hw_id.word = dev->reg->ID.word; |
| 280 | |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 281 | LOG_INFO("Optimizer config. cmd_stream_version=%d, macs_per_cc=%d, shram_size=%d, custom_dma=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 282 | opt_cfg->cmd_stream_version, |
| 283 | opt_cfg->macs_per_cc, |
| 284 | opt_cfg->shram_size, |
| 285 | opt_cfg->custom_dma); |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 286 | LOG_INFO("Optimizer config. Ethos-U version: %d.%d.%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 287 | opt_id->arch_major_rev, |
| 288 | opt_id->arch_minor_rev, |
| 289 | opt_id->arch_patch_rev); |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 290 | LOG_INFO("Ethos-U config. cmd_stream_version=%d, macs_per_cc=%d, shram_size=%d, custom_dma=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 291 | hw_cfg.cmd_stream_version, |
| 292 | hw_cfg.macs_per_cc, |
| 293 | hw_cfg.shram_size, |
| 294 | hw_cfg.custom_dma); |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 295 | LOG_INFO("Ethos-U. version=%d.%d.%d", hw_id.arch_major_rev, hw_id.arch_minor_rev, hw_id.arch_patch_rev); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 296 | |
| 297 | if (opt_cfg->word != hw_cfg.word) |
| 298 | { |
| 299 | if (hw_cfg.macs_per_cc != opt_cfg->macs_per_cc) |
| 300 | { |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 301 | LOG_ERR("NPU config mismatch. npu.macs_per_cc=%d, optimizer.macs_per_cc=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 302 | hw_cfg.macs_per_cc, |
| 303 | opt_cfg->macs_per_cc); |
| 304 | ret = false; |
| 305 | } |
| 306 | |
| 307 | if (hw_cfg.shram_size != opt_cfg->shram_size) |
| 308 | { |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 309 | LOG_ERR("NPU config mismatch. npu.shram_size=%d, optimizer.shram_size=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 310 | hw_cfg.shram_size, |
| 311 | opt_cfg->shram_size); |
| 312 | ret = false; |
| 313 | } |
| 314 | |
| 315 | if (hw_cfg.cmd_stream_version != opt_cfg->cmd_stream_version) |
| 316 | { |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 317 | LOG_ERR("NPU config mismatch. npu.cmd_stream_version=%d, optimizer.cmd_stream_version=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 318 | hw_cfg.cmd_stream_version, |
| 319 | opt_cfg->cmd_stream_version); |
| 320 | ret = false; |
| 321 | } |
| 322 | |
| 323 | if (!hw_cfg.custom_dma && opt_cfg->custom_dma) |
| 324 | { |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 325 | LOG_ERR("NPU config mismatch. npu.custom_dma=%d, optimizer.custom_dma=%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 326 | hw_cfg.custom_dma, |
| 327 | opt_cfg->custom_dma); |
| 328 | ret = false; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | if ((hw_id.arch_major_rev != opt_id->arch_major_rev) || (hw_id.arch_minor_rev < opt_id->arch_minor_rev)) |
| 333 | { |
Kristofer Jonsson | 1975b8d | 2021-11-26 16:15:44 +0100 | [diff] [blame^] | 334 | LOG_ERR("NPU arch mismatch. npu.arch=%d.%d.%d, optimizer.arch=%d.%d.%d", |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame] | 335 | hw_id.arch_major_rev, |
| 336 | hw_id.arch_minor_rev, |
| 337 | hw_id.arch_patch_rev, |
| 338 | opt_id->arch_major_rev, |
| 339 | opt_id->arch_minor_rev, |
| 340 | opt_id->arch_patch_rev); |
| 341 | ret = false; |
| 342 | } |
| 343 | |
| 344 | return ret; |
| 345 | } |