Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 19 | #ifndef PMU_ETHOSU_H |
| 20 | #define PMU_ETHOSU_H |
| 21 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 22 | #include <stdint.h> |
| 23 | |
| 24 | #ifdef __cplusplus |
| 25 | extern "C" { |
| 26 | #endif |
| 27 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 28 | #define ETHOSU_PMU_NCOUNTERS 4 |
| 29 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 30 | /** \brief HW Supported ETHOSU PMU Events |
| 31 | * |
| 32 | * Note: These values are symbolic. Actual HW-values may change. I.e. always use API |
| 33 | * to set/get actual event-type value. |
| 34 | * */ |
| 35 | enum ethosu_pmu_event_type |
| 36 | { |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 37 | ETHOSU_PMU_NO_EVENT = 0, |
| 38 | ETHOSU_PMU_CYCLE, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 39 | ETHOSU_PMU_NPU_IDLE, |
Douglas Troha | f6a85da | 2020-05-11 11:45:28 +0200 | [diff] [blame] | 40 | ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, |
| 41 | ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, |
Douglas Troha | 2407e96 | 2020-06-15 14:31:45 +0200 | [diff] [blame] | 42 | ETHOSU_PMU_NPU_ACTIVE, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 43 | ETHOSU_PMU_MAC_ACTIVE, |
| 44 | ETHOSU_PMU_MAC_ACTIVE_8BIT, |
| 45 | ETHOSU_PMU_MAC_ACTIVE_16BIT, |
| 46 | ETHOSU_PMU_MAC_DPU_ACTIVE, |
| 47 | ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, |
| 48 | ETHOSU_PMU_MAC_STALLED_BY_WD, |
| 49 | ETHOSU_PMU_MAC_STALLED_BY_ACC, |
| 50 | ETHOSU_PMU_MAC_STALLED_BY_IB, |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 51 | ETHOSU_PMU_MAC_ACTIVE_32BIT, |
Douglas Troha | f6a85da | 2020-05-11 11:45:28 +0200 | [diff] [blame] | 52 | ETHOSU_PMU_MAC_STALLED_BY_INT_W, |
| 53 | ETHOSU_PMU_MAC_STALLED_BY_INT_ACC, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 54 | ETHOSU_PMU_AO_ACTIVE, |
| 55 | ETHOSU_PMU_AO_ACTIVE_8BIT, |
| 56 | ETHOSU_PMU_AO_ACTIVE_16BIT, |
| 57 | ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, |
| 58 | ETHOSU_PMU_AO_STALLED_BY_OFMP, |
| 59 | ETHOSU_PMU_AO_STALLED_BY_OB, |
| 60 | ETHOSU_PMU_AO_STALLED_BY_ACC_IB, |
| 61 | ETHOSU_PMU_AO_STALLED_BY_ACC, |
| 62 | ETHOSU_PMU_AO_STALLED_BY_IB, |
| 63 | ETHOSU_PMU_WD_ACTIVE, |
| 64 | ETHOSU_PMU_WD_STALLED, |
| 65 | ETHOSU_PMU_WD_STALLED_BY_WS, |
| 66 | ETHOSU_PMU_WD_STALLED_BY_WD_BUF, |
| 67 | ETHOSU_PMU_WD_PARSE_ACTIVE, |
| 68 | ETHOSU_PMU_WD_PARSE_STALLED, |
| 69 | ETHOSU_PMU_WD_PARSE_STALLED_IN, |
| 70 | ETHOSU_PMU_WD_PARSE_STALLED_OUT, |
Diqing Zhong | 25e2c81 | 2020-04-27 13:47:25 +0200 | [diff] [blame] | 71 | ETHOSU_PMU_WD_TRANS_WS, |
| 72 | ETHOSU_PMU_WD_TRANS_WB, |
| 73 | ETHOSU_PMU_WD_TRANS_DW0, |
| 74 | ETHOSU_PMU_WD_TRANS_DW1, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 75 | ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, |
| 76 | ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, |
| 77 | ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, |
| 78 | ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, |
| 79 | ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, |
| 80 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, |
| 81 | ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, |
| 82 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, |
| 83 | ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, |
| 84 | ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, |
| 85 | ETHOSU_PMU_AXI0_ENABLED_CYCLES, |
| 86 | ETHOSU_PMU_AXI0_RD_STALL_LIMIT, |
| 87 | ETHOSU_PMU_AXI0_WR_STALL_LIMIT, |
| 88 | ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, |
| 89 | ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, |
| 90 | ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, |
| 91 | ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, |
| 92 | ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, |
| 93 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, |
| 94 | ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, |
| 95 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, |
| 96 | ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, |
| 97 | ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, |
| 98 | ETHOSU_PMU_AXI1_ENABLED_CYCLES, |
| 99 | ETHOSU_PMU_AXI1_RD_STALL_LIMIT, |
| 100 | ETHOSU_PMU_AXI1_WR_STALL_LIMIT, |
| 101 | ETHOSU_PMU_AXI_LATENCY_ANY, |
| 102 | ETHOSU_PMU_AXI_LATENCY_32, |
| 103 | ETHOSU_PMU_AXI_LATENCY_64, |
| 104 | ETHOSU_PMU_AXI_LATENCY_128, |
| 105 | ETHOSU_PMU_AXI_LATENCY_256, |
| 106 | ETHOSU_PMU_AXI_LATENCY_512, |
| 107 | ETHOSU_PMU_AXI_LATENCY_1024, |
| 108 | |
| 109 | ETHOSU_PMU_SENTINEL // End-marker (not event) |
| 110 | }; |
| 111 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 112 | #define ETHOSU_PMU_CNT1_Msk (1UL << 0) |
| 113 | #define ETHOSU_PMU_CNT2_Msk (1UL << 1) |
| 114 | #define ETHOSU_PMU_CNT3_Msk (1UL << 2) |
| 115 | #define ETHOSU_PMU_CNT4_Msk (1UL << 3) |
| 116 | #define ETHOSU_PMU_CCNT_Msk (1UL << 31) |
| 117 | |
| 118 | /* Transpose functions between HW-event-type and event-id*/ |
| 119 | enum ethosu_pmu_event_type pmu_event_type(uint32_t); |
| 120 | uint32_t pmu_event_value(enum ethosu_pmu_event_type); |
| 121 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 122 | /* Initialize the PMU driver */ |
| 123 | void ethosu_pmu_driver_init(void); |
| 124 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 125 | // CMSIS ref API |
| 126 | /** \brief PMU Functions */ |
| 127 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 128 | /** |
| 129 | \brief Enable the PMU |
| 130 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 131 | void ETHOSU_PMU_Enable(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 132 | |
| 133 | /** |
| 134 | \brief Disable the PMU |
| 135 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 136 | void ETHOSU_PMU_Disable(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 137 | |
| 138 | /** |
| 139 | \brief Set event to count for PMU eventer counter |
| 140 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 141 | \param [in] type Event to count |
| 142 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 143 | void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 144 | |
| 145 | /** |
| 146 | \brief Get event to count for PMU eventer counter |
| 147 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure |
| 148 | \return type Event to count |
| 149 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 150 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 151 | |
| 152 | /** |
| 153 | \brief Reset cycle counter |
| 154 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 155 | void ETHOSU_PMU_CYCCNT_Reset(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 156 | |
| 157 | /** |
| 158 | \brief Reset all event counters |
| 159 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 160 | void ETHOSU_PMU_EVCNTR_ALL_Reset(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 161 | |
| 162 | /** |
| 163 | \brief Enable counters |
| 164 | \param [in] mask Counters to enable |
| 165 | \note Enables one or more of the following: |
| 166 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 167 | - cycle counter (bit 31) |
| 168 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 169 | void ETHOSU_PMU_CNTR_Enable(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 170 | |
| 171 | /** |
| 172 | \brief Disable counters |
| 173 | \param [in] mask Counters to disable |
| 174 | \note Disables one or more of the following: |
| 175 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 176 | - cycle counter (bit 31) |
| 177 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 178 | void ETHOSU_PMU_CNTR_Disable(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 179 | |
| 180 | /** |
| 181 | \brief Determine counters activation |
| 182 | |
| 183 | \return Event count |
| 184 | \param [in] mask Counters to enable |
| 185 | \return a bitmask where bit-set means: |
| 186 | - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 187 | - cycle counter activate (bit 31) |
| 188 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 189 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 190 | uint32_t ETHOSU_PMU_CNTR_Status(); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 191 | |
| 192 | /** |
| 193 | \brief Read cycle counter (64 bit) |
| 194 | \return Cycle count |
| 195 | \note Two HW 32-bit registers that can increment independently in-between reads. |
| 196 | To work-around raciness yet still avoid turning |
| 197 | off the event both are read as one value twice. If the latter read |
| 198 | is not greater than the former, it means overflow of LSW without |
| 199 | incrementing MSW has occurred, in which case the former value is used. |
| 200 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 201 | uint64_t ETHOSU_PMU_Get_CCNTR(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 202 | |
| 203 | /** |
| 204 | \brief Set cycle counter (64 bit) |
| 205 | \param [in] val Conter value |
| 206 | \note Two HW 32-bit registers that can increment independently in-between reads. |
| 207 | To work-around raciness, counter is temporary disabled if enabled. |
| 208 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 209 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 210 | void ETHOSU_PMU_Set_CCNTR(uint64_t val); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 211 | |
| 212 | /** |
| 213 | \brief Read event counter |
| 214 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 215 | \return Event count |
| 216 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 217 | uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 218 | |
| 219 | /** |
| 220 | \brief Set event counter value |
| 221 | \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) |
| 222 | \param [in] val Conter value |
| 223 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 224 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 225 | void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val); |
| 226 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 227 | /** |
| 228 | \brief Read counter overflow status |
| 229 | \return Counter overflow status bits for the following: |
| 230 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) |
| 231 | - cycle counter (bit 31) |
| 232 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 233 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 234 | |
| 235 | /** |
| 236 | \brief Clear counter overflow status |
| 237 | \param [in] mask Counter overflow status bits to clear |
| 238 | \note Clears overflow status bits for one or more of the following: |
| 239 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 240 | - cycle counter (bit 31) |
| 241 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 242 | void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 243 | |
| 244 | /** |
| 245 | \brief Enable counter overflow interrupt request |
| 246 | \param [in] mask Counter overflow interrupt request bits to set |
| 247 | \note Sets overflow interrupt request bits for one or more of the following: |
| 248 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 249 | - cycle counter (bit 31) |
| 250 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 251 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 252 | |
| 253 | /** |
| 254 | \brief Disable counter overflow interrupt request |
| 255 | \param [in] mask Counter overflow interrupt request bits to clear |
| 256 | \note Clears overflow interrupt request bits for one or more of the following: |
| 257 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 258 | - cycle counter (bit 31) |
| 259 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 260 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 261 | |
| 262 | /** |
| 263 | \brief Get counters overflow interrupt request stiinings |
| 264 | \return mask Counter overflow interrupt request bits |
| 265 | \note Sets overflow interrupt request bits for one or more of the following: |
| 266 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 267 | - cycle counter (bit 31) |
| 268 | \note ETHOSU specific. Usage breaks CMSIS complience |
| 269 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 270 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 271 | |
| 272 | /** |
| 273 | \brief Software increment event counter |
| 274 | \param [in] mask Counters to increment |
| 275 | - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) |
| 276 | - cycle counter (bit 31) |
| 277 | \note Software increment bits for one or more event counters. |
| 278 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 279 | void ETHOSU_PMU_CNTR_Increment(uint32_t mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 280 | |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 281 | /** |
| 282 | \brief Set start event number for the cycle counter |
| 283 | \param [in] start_event Event number |
| 284 | - Start event (bits [9:0]) |
| 285 | \note Sets the event number that starts the cycle counter. |
| 286 | - Event number in the range 0..1023 |
| 287 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 288 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event); |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 289 | |
| 290 | /** |
| 291 | \brief Set stop event number for the cycle counter |
| 292 | \param [in] stop_event Event number |
| 293 | - Stop event (bits [25:16]) |
| 294 | \note Sets the event number that stops the cycle counter. |
| 295 | - Event number in the range 0..1023 |
| 296 | */ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame^] | 297 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event); |
Bhavik Patel | 4e8dbf5 | 2020-06-15 10:09:28 +0200 | [diff] [blame] | 298 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 299 | #ifdef __cplusplus |
| 300 | } |
| 301 | #endif |
| 302 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 303 | #endif /* PMU_ETHOSU_H */ |