blob: 7c33470daececbc272d825c97049cbdcd520614d [file] [log] [blame]
Kristofer Jonsson49bdee82020-04-06 13:21:21 +02001/*
2 * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#if !defined ETHOSU_COMMON_H
20#define ETHOSU_COMMON_H
21
22#include "ethosu55_interface.h"
23
24#if !defined(LOG_ENABLED)
25#define LOG_INFO(format, ...)
26#define LOG_ERR(format, ...)
27#else
28#define LOG_INFO(format, ...) fprintf(stdout, format, ##__VA_ARGS__)
29#define LOG_ERR(format, ...) \
30 fprintf(stderr, format, ##__VA_ARGS__); \
31 fflush(stderr)
32
33#endif
34
35#if defined(ASSERT_DISABLE)
36#define ASSERT(args)
37#else
38#define ASSERT(args) assert(args)
39#endif
40
41#if defined(CPU_CORTEX_M55)
42#define NPU_BASE ((uint32_t)0x41700000)
43#else
44#define NPU_BASE ((uint32_t)0x41105000)
45#endif
46#define UNUSED(x) ((void)x)
47
48#define VER_STR(X) VNUM_STR(X)
49#define VNUM_STR(X) #X
50
Bhavik Patel8e32b0b2020-06-23 13:48:25 +020051#define MASK_0_31_BITS (0xFFFFFFFF)
52#define MASK_32_47_BITS (0xFFFF00000000)
53
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020054static const __attribute__((section("npu_driver_version"))) char driver_version_str[] = VER_STR(
55 ETHOSU_DRIVER_VERSION_MAJOR) "." VER_STR(ETHOSU_DRIVER_VERSION_MINOR) "." VER_STR(ETHOSU_DRIVER_VERSION_PATCH);
56
57static const __attribute__((section("npu_driver_arch_version"))) char driver_arch_version_str[] =
58 VER_STR(NNX_ARCH_VERSION_MAJOR) "." VER_STR(NNX_ARCH_VERSION_MINOR) "." VER_STR(NNX_ARCH_VERSION_PATCH);
59
60static inline uint32_t read_reg(uint32_t address)
61{
62 volatile uint32_t *reg = (uint32_t *)(uintptr_t)(NPU_BASE + address);
63 return *reg;
64}
65
66static inline void write_reg(uint32_t address, uint32_t value)
67{
68 volatile uint32_t *reg = (uint32_t *)(uintptr_t)(NPU_BASE + address);
69 *reg = value;
70}
71
72#endif // ETHOSU_COMMON_H