| Jonny Svärd | b64628f | 2020-06-02 15:24:54 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | #ifndef ETHOSU_CONFIG_H |
| 20 | #define ETHOSU_CONFIG_H |
| 21 | |
| 22 | /* Set default values if not manually overriden */ |
| 23 | |
| 24 | #ifndef NPU_QCONFIG |
| 25 | #define NPU_QCONFIG 2 |
| 26 | #endif |
| 27 | |
| 28 | #ifndef NPU_REGIONCFG_0 |
| 29 | #define NPU_REGIONCFG_0 3 |
| 30 | #endif |
| 31 | |
| 32 | #ifndef NPU_REGIONCFG_1 |
| 33 | #define NPU_REGIONCFG_1 0 |
| 34 | #endif |
| 35 | |
| 36 | #ifndef NPU_REGIONCFG_2 |
| 37 | #define NPU_REGIONCFG_2 1 |
| 38 | #endif |
| 39 | |
| 40 | #ifndef NPU_REGIONCFG_3 |
| 41 | #define NPU_REGIONCFG_3 1 |
| 42 | #endif |
| 43 | |
| 44 | #ifndef NPU_REGIONCFG_4 |
| 45 | #define NPU_REGIONCFG_4 1 |
| 46 | #endif |
| 47 | |
| 48 | #ifndef NPU_REGIONCFG_5 |
| 49 | #define NPU_REGIONCFG_5 1 |
| 50 | #endif |
| 51 | |
| 52 | #ifndef NPU_REGIONCFG_6 |
| 53 | #define NPU_REGIONCFG_6 1 |
| 54 | #endif |
| 55 | |
| 56 | #ifndef NPU_REGIONCFG_7 |
| 57 | #define NPU_REGIONCFG_7 1 |
| 58 | #endif |
| 59 | |
| 60 | #ifndef AXI_LIMIT0_MAX_BEATS_BYTES |
| 61 | #define AXI_LIMIT0_MAX_BEATS_BYTES 0x0 |
| 62 | #endif |
| 63 | #ifndef AXI_LIMIT0_MEM_TYPE |
| 64 | #define AXI_LIMIT0_MEM_TYPE 0x0 |
| 65 | #endif |
| 66 | #ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS |
| 67 | #define AXI_LIMIT0_MAX_OUTSTANDING_READS 32 |
| 68 | #endif |
| 69 | #ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES |
| 70 | #define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 16 |
| 71 | #endif |
| 72 | |
| 73 | #ifndef AXI_LIMIT1_MAX_BEATS_BYTES |
| 74 | #define AXI_LIMIT1_MAX_BEATS_BYTES 0x0 |
| 75 | #endif |
| 76 | #ifndef AXI_LIMIT1_MEM_TYPE |
| 77 | #define AXI_LIMIT1_MEM_TYPE 0x0 |
| 78 | #endif |
| 79 | #ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS |
| 80 | #define AXI_LIMIT1_MAX_OUTSTANDING_READS 32 |
| 81 | #endif |
| 82 | #ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES |
| 83 | #define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 16 |
| 84 | #endif |
| 85 | |
| 86 | #ifndef AXI_LIMIT2_MAX_BEATS_BYTES |
| 87 | #define AXI_LIMIT2_MAX_BEATS_BYTES 0x0 |
| 88 | #endif |
| 89 | #ifndef AXI_LIMIT2_MEM_TYPE |
| 90 | #define AXI_LIMIT2_MEM_TYPE 0x0 |
| 91 | #endif |
| 92 | #ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS |
| 93 | #define AXI_LIMIT2_MAX_OUTSTANDING_READS 32 |
| 94 | #endif |
| 95 | #ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES |
| 96 | #define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 16 |
| 97 | #endif |
| 98 | #ifndef AXI_LIMIT3_MAX_BEATS_BYTES |
| 99 | #define AXI_LIMIT3_MAX_BEATS_BYTES 0x0 |
| 100 | #endif |
| 101 | #ifndef AXI_LIMIT3_MEM_TYPE |
| 102 | #define AXI_LIMIT3_MEM_TYPE 0x0 |
| 103 | #endif |
| 104 | #ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS |
| 105 | #define AXI_LIMIT3_MAX_OUTSTANDING_READS 32 |
| 106 | #endif |
| 107 | #ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES |
| 108 | #define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 16 |
| 109 | #endif |
| 110 | |
| 111 | #ifdef PMU_AUTOINIT |
| 112 | /* |
| 113 | * Register control |
| 114 | * b0 = CNT_EN = Enable counters (RW) |
| 115 | * b1 = EVENT_CNT_RST = Reset event counters (WO) |
| 116 | * b2 = CYCLE_CNT_RST = Reset cycle counter (WO) |
| 117 | * b[15:11] = Number of event counters (RO) |
| 118 | */ |
| 119 | #ifndef INIT_PMCR |
| 120 | #define INIT_PMCR 0x0 |
| 121 | #endif |
| 122 | |
| 123 | /* |
| 124 | * Bit k enables event counter k |
| 125 | * k=31 enables the cycle counter |
| 126 | * Read value is current status |
| 127 | */ |
| 128 | #ifndef INIT_PMCNTENSET |
| 129 | #define INIT_PMCNTENSET 0x0 |
| 130 | #endif |
| 131 | |
| 132 | /* |
| 133 | * Bit k disables event counter k |
| 134 | * k=31 disables the cycle counter |
| 135 | * Read value is current status |
| 136 | */ |
| 137 | #ifndef INIT_PMCNTENCLR |
| 138 | #define INIT_PMCNTENCLR 0x0 |
| 139 | #endif |
| 140 | |
| 141 | /* |
| 142 | * Overflow detection set |
| 143 | * Bit k is for counter k |
| 144 | * k=31 is cycle counter |
| 145 | */ |
| 146 | #ifndef INIT_PMOVSSET |
| 147 | #define INIT_PMOVSSET 0x0 |
| 148 | #endif |
| 149 | |
| 150 | /* |
| 151 | * Overflow detection clear |
| 152 | * Bit k is for counter k |
| 153 | * k=31 is cycle counter |
| 154 | */ |
| 155 | #ifndef INIT_PMOVSCLR |
| 156 | #define INIT_PMOVSCLR 0x0 |
| 157 | #endif |
| 158 | |
| 159 | /* |
| 160 | * Interrupt set |
| 161 | * Bit k is for counter k |
| 162 | * k=31 is cycle counter |
| 163 | */ |
| 164 | #ifndef INIT_PMINTSET |
| 165 | #define INIT_PMINTSET 0x0 |
| 166 | #endif |
| 167 | |
| 168 | /* |
| 169 | * Interrupt clear |
| 170 | * Bit k is for counter k |
| 171 | * k=31 is cycle counter |
| 172 | */ |
| 173 | #ifndef INIT_PMINTCLR |
| 174 | #define INIT_PMINTCLR 0x8003 |
| 175 | #endif |
| 176 | |
| 177 | /* Cycle counter |
| 178 | * 48 bits value |
| 179 | */ |
| 180 | #ifndef INIT_PMCCNTR |
| 181 | #define INIT_PMCCNTR 0x0 |
| 182 | #endif |
| 183 | |
| 184 | /* |
| 185 | * b[9:0] Start Event – this event number starts the cycle counter |
| 186 | * b[25:16] Stop Event – this event number stops the cycle counter |
| 187 | */ |
| 188 | #ifndef INIT_PMCCNTR_CFG |
| 189 | #define INIT_PMCCNTR_CFG 0x0 |
| 190 | #endif |
| 191 | |
| 192 | #endif /* #ifdef PMU_AUTOINIT */ |
| 193 | |
| 194 | #endif /* #ifndef ETHOSU_CONFIG_H */ |