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Kristofer Jonsson49bdee82020-04-06 13:21:21 +02001/*
2 * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#pragma once
20
21/******************************************************************************
22 * Includes
23 ******************************************************************************/
24
25#include <stdint.h>
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/******************************************************************************
32 * Defines
33 ******************************************************************************/
34
35#define ETHOSU_DRIVER_VERSION_MAJOR 0 ///< Driver major version
Douglas Trohaf6a85da2020-05-11 11:45:28 +020036#define ETHOSU_DRIVER_VERSION_MINOR 16 ///< Driver minor version
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020037#define ETHOSU_DRIVER_VERSION_PATCH 0 ///< Driver patch version
38#define ETHOSU_DRIVER_BASEP_INDEXES 8 ///< Number of base pointer indexes
39
40/******************************************************************************
41 * Types
42 ******************************************************************************/
43
44enum ethosu_error_codes
45{
46 ETHOSU_SUCCESS = 0, ///< Success
47 ETHOSU_GENERIC_FAILURE = -1, ///< Generic failure
48 ETHOSU_INVALID_PARAM = -2 ///< Invalid parameter
49};
50
Bhavik Pateldae5be02020-06-18 15:25:15 +020051struct ethosu_device
52{
53 uintptr_t base_address;
54};
55
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020056struct ethosu_id
57{
58 uint32_t version_status; ///< Version status
59 uint32_t version_minor; ///< Version minor
60 uint32_t version_major; ///< Version major
61 uint32_t product_major; ///< Product major
62 uint32_t arch_patch_rev; ///< Architecture version patch
63 uint32_t arch_minor_rev; ///< Architecture version minor
64 uint32_t arch_major_rev; ///< Architecture version major
65};
66
67struct ethosu_config
68{
69 struct
70 {
71 uint32_t macs_per_cc; ///< MACs per clock cycle
72 uint32_t cmd_stream_version; ///< NPU command stream version
73 uint32_t shram_size; ///< SHRAM size
74 };
75};
76
77/**
78 * Memory type parameter for set_regioncfg_reg:
79 * Counter{0,1}: Outstanding transactions for
80 * AXI port 0 for memory type/region a=0,b=1
81 * Counter{2,3}: Outstanding transactions for
82 * AXI port 1 for memory type/region a=2,b=3
83 */
84enum ethosu_memory_type
85{
86 ETHOSU_AXI0_OUTSTANDING_COUNTER0 = 0, ///< NPU axi0_outstanding_counter0
87 ETHOSU_AXI0_OUTSTANDING_COUNTER1 = 1, ///< NPU axi0_outstanding_counter1
88 ETHOSU_AXI1_OUTSTANDING_COUNTER2 = 2, ///< NPU axi1_outstanding_counter2
89 ETHOSU_AXI1_OUTSTANDING_COUNTER3 = 3 ///< NPU axi1_outstanding_counter3
90};
91
92enum ethosu_axi_limit_beats
93{
94 ETHOSU_AXI_LIMIT_64_BYTES = 0, ///< NPU AXI limit 64 byte burst split alignment.
95 ETHOSU_AXI_LIMIT_128_BYTES = 1, ///< NPU AXI limit 128 byte burst split alignment.
96 ETHOSU_AXI_LIMIT_256_BYTES = 2 ///< NPU AXI limit 256 byte burst split alignment.
97};
98
99enum ethosu_axi_limit_mem_type
100{
101 ETHOSU_MEM_TYPE_DEVICE_NON_BUFFERABLE = 0,
102 ETHOSU_MEM_TYPE_DEVICE_BUFFERABLE = 1,
103 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2,
104 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_BUFFERABLE = 3,
105 ETHOSU_MEM_TYPE_WRITE_THROUGH_NO_ALLOCATE = 4,
106 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_ALLOCATE = 5,
107 ETHOSU_MEM_TYPE_WRITE_THROUGH_WRITE_ALLOCATE = 6,
108 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
109 ETHOSU_MEM_TYPE_WRITE_BACK_NO_ALLOCATE = 8,
110 ETHOSU_MEM_TYPE_WRITE_BACK_READ_ALLOCATE = 9,
111 ETHOSU_MEM_TYPE_WRITE_BACK_WRITE_ALLOCATE = 10,
112 ETHOSU_MEM_TYPE_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11
113};
114
115enum ethosu_clock_q_request
116{
117 ETHOSU_CLOCK_Q_DISABLE = 0, ///< Disble NPU signal ready for clock off.
118 ETHOSU_CLOCK_Q_ENABLE = 1 ///< Enable NPU signal ready for clock off when stop+idle state reached.
119};
120
121enum ethosu_power_q_request
122{
123 ETHOSU_POWER_Q_DISABLE = 0, ///< Disble NPU signal ready for power off.
124 ETHOSU_POWER_Q_ENABLE = 1 ///< Enable NPU signal ready for power off when stop+idle state reached.
125};
126
127/******************************************************************************
128 * Prototypes
129 ******************************************************************************/
130
131/**
132 * Initialize the device.
133 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200134enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, const void *base_address);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200135
136/**
137 * Get device id.
138 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200139enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200140
141/**
142 * Get device configuration.
143 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200144enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200145
146/**
147 * Execute a given command stream on NPU.
148 * \param[in] cmd_stream_ptr Pointer to the command stream
149 * \param[in] cms_length Command stream length
150 * \param[in] base_addr Pointer to array of base addresses
151 * - 0: weight tensor
152 * - 1: scratch tensor
153 * - All input tensors
154 * - All output tensors
155 * \param[in] num_base_addr Number of base addresses.
156 * \return \ref ethosu_error_codes
157 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200158enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
159 const uint8_t *cmd_stream_ptr,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200160 uint32_t cms_length,
161 const uint64_t *base_addr,
162 int num_base_addr);
163
164/**
165 * Check if IRQ is raised.
166 * \param[out] irq_status Pointer to IRQ status
167 * - 0 IRQ not raised
168 * - 1 IRQ raised
169 * \return \ref ethosu_error_codes
170 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200171enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_status);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200172
173/**
174 * Clear IRQ status.
175 * \return \ref ethosu_error_codes
176 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200177enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200178
179/**
180 * Get the 16 bit status mask.
181 * \param[out] irq_status_mask Pointer to the status mask.
182 * The lower 16 bits of status reg are returned.
183 * bit0: state
184 * bit1: irq_raised
185 * bit2: bus_status
186 * bit3: reset_status
187 * bit4: cmd_parse_error
188 * bit5: cmd_end_reached
189 * bit6: pmu_irq_raised
190 * bit7-15: reserved
191 * \return \ref ethosu_error_codes
192 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200193enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200194
195/**
196 * Get the 16 bit IRQ history mask.
197 * \param[out] irq_history_mask Pointer to the IRQ history mask.
198 * \return \ref ethosu_error_codes
199 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200200enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200201
202/**
203 * Clear the given bits in the
204 * IRQ history mask.
205 * \param[in] irq_history_clear_mask 16 bit mask indicating which bits to
206 * clear in the IRQ history mask.
207 * \return \ref ethosu_error_codes
208 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200209enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200210
211/**
212 * Perform a NPU soft reset.
213 * \return \ref ethosu_error_codes
214 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200215enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200216
217/**
218 * Wait for reset ready.
219 * \return \ref ethosu_error_codes
220 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200221enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200222
223/**
224 * Read and return the content of a given NPU APB
225 * register range.
226 * \param[in] start_address Start address.
227 * \param[in] num_reg Number of registers to read.
228 * \param[out] reg_p Pointer to a output area, allocated by the
229 * caller, where the register content shall be
230 * written.
231 * \return \ref ethosu_error_codes
232 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200233enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev,
234 uint32_t start_address,
235 uint16_t num_reg,
236 uint32_t *reg_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200237
238/**
239 * Set qconfig register. I.e.
240 * AXI configuration for the command stream.
241 * \param[in] memory_type Memory_type to use for command stream:
242 * enum ethosu_memory_type.
243 * \return \ref ethosu_error_codes
244 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200245enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200246
247/**
248 * Set register REGIONCFG.
249 * Base pointer configuration.
250 * Bits[2*k+1:2*k] give the memory type for BASEP[k].
251 * \param[in] region Region field to set: 0 - 7.
252 * \param[in] memory_type Memory_type to use for region: enum ethosu_memory_type.
253 * \return \ref ethosu_error_codes
254 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200255enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev,
256 uint8_t region,
257 enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200258
259/**
260 * Set AXI limit parameters for port 0 counter 0.
261 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
262 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
263 * \param[in] max_reads Maximum number of outstanding reads.
264 * \param[in] max_writes Maximum number of outstanding writes.
265 * \return \ref ethosu_error_codes
266 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200267enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev,
268 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200269 enum ethosu_axi_limit_mem_type memtype,
270 uint8_t max_reads,
271 uint8_t max_writes);
272/**
273 * Set AXI limit parameters for port 0 counter 1.
274 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
275 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
276 * \param[in] max_reads Maximum number of outstanding reads.
277 * \param[in] max_writes Maximum number of outstanding writes.
278 * \return \ref ethosu_error_codes
279 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200280enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev,
281 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200282 enum ethosu_axi_limit_mem_type memtype,
283 uint8_t max_reads,
284 uint8_t max_writes);
285/**
286 * Set AXI limit parameters for port 1 counter 2.
287 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
288 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
289 * \param[in] max_reads Maximum number of outstanding reads.
290 * \param[in] max_writes Maximum number of outstanding writes.
291 * \return \ref ethosu_error_codes
292 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200293enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev,
294 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200295 enum ethosu_axi_limit_mem_type memtype,
296 uint8_t max_reads,
297 uint8_t max_writes);
298/**
299 * Set AXI limit parameters for port 1 counter 3.
300 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
301 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
302 * \param[in] max_reads Maximum number of outstanding reads.
303 * \param[in] max_writes Maximum number of outstanding writes.
304 * \return \ref ethosu_error_codes
305 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200306enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev,
307 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200308 enum ethosu_axi_limit_mem_type memtype,
309 uint8_t max_reads,
310 uint8_t max_writes);
311
312/**
313 * Get current command stream queue read position.
314 * \param[out] qread Pointer to queue read.
315 * \return \ref ethosu_error_codes
316 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200317enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200318
319/**
320 * Get revision of NPU
321 * \param[out] revision Pointer to revision read.
322 * \return \ref ethosu_error_codes
323 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200324enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200325
326/**
327 * Issue run command for the currently programmed
328 * command stream, starting at current queue read
329 * position.
330 * \return \ref ethosu_error_codes
331 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200332enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200333
334/**
335 * Dump a 1KB section of SHRAM.
336 * \param[in] section Section offset to 1KB section in SHRAM.
337 * \param[out] shram_p Pointer to a output area, allocated by the
338 * caller, where the SHRAM content shall be
339 * written.
340 * \return \ref ethosu_error_codes
341 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200342enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200343
344/**
345 * Set clock and power q request enable bits.
346 * \param[in] clock_q Clock q ENABLE/DISABLE \ref clock_q_request.
347 * \param[in] power_q Power q ENABLE/DISABLE \ref power_q_request.
348 * \return \ref ethosu_error_codes
349 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200350enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev,
351 enum ethosu_clock_q_request clock_q,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200352 enum ethosu_power_q_request power_q);
353
Bhavik Pateldae5be02020-06-18 15:25:15 +0200354uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address);
355
356void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value);
357
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200358#ifdef __cplusplus
359}
360#endif