Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
| 23 | #include "ethosu55_interface.h" |
| 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 25 | #include "ethosu_driver.h" |
| 26 | #include "pmu_ethosu.h" |
| 27 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 29 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 30 | #include <stdint.h> |
| 31 | |
| 32 | /***************************************************************************** |
| 33 | * Defines |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #define COMMA , |
| 37 | #define SEMICOLON ; |
| 38 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 39 | #define EVTYPE(A, name) \ |
| 40 | case PMU_EVENT_TYPE_##name: \ |
| 41 | return ETHOSU_PMU_##name |
| 42 | |
| 43 | #define EVID(A, name) (PMU_EVENT_TYPE_##name) |
| 44 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 45 | #define ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK (0x3FF) |
| 46 | |
| 47 | #define NPU_REG_PMEVCNTR(x) (NPU_REG_PMEVCNTR0 + ((x) * sizeof(uint32_t))) |
| 48 | #define NPU_REG_PMEVTYPER(x) (NPU_REG_PMEVTYPER0 + ((x) * sizeof(uint32_t))) |
| 49 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 50 | /***************************************************************************** |
| 51 | * Variables |
| 52 | *****************************************************************************/ |
| 53 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 54 | /** |
| 55 | * NOTE: A pointer to ethosu_driver will be added to the PMU functions |
| 56 | * when multi-NPU functionality is implemented later. We shall use a |
| 57 | * shared ethosu_driver instance till then. |
| 58 | * */ |
| 59 | extern struct ethosu_driver ethosu_drv; |
| 60 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 61 | static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)}; |
| 62 | |
| 63 | /***************************************************************************** |
| 64 | * Functions |
| 65 | *****************************************************************************/ |
| 66 | |
| 67 | enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
| 68 | { |
| 69 | switch (id) |
| 70 | { |
| 71 | EXPAND_PMU_EVENT_TYPE(EVTYPE, SEMICOLON); |
| 72 | } |
| 73 | |
| 74 | return ETHOSU_PMU_SENTINEL; |
| 75 | } |
| 76 | |
| 77 | uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
| 78 | { |
| 79 | if (!(event < ETHOSU_PMU_SENTINEL) || (event < 0)) |
| 80 | { |
| 81 | return (uint32_t)(-1); |
| 82 | } |
| 83 | |
| 84 | return eventbyid[event]; |
| 85 | } |
| 86 | |
| 87 | void ethosu_pmu_driver_init(void) |
| 88 | { |
| 89 | #ifdef PMU_AUTOINIT |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 90 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, INIT_PMCR); |
| 91 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, INIT_PMCNTENSET); |
| 92 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, INIT_PMCNTENCLR); |
| 93 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSSET, INIT_PMOVSSET); |
| 94 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, INIT_PMOVSCLR); |
| 95 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, INIT_PMINTSET); |
| 96 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, INIT_PMINTCLR); |
| 97 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, INIT_PMCCNTR); |
| 98 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, INIT_PMCCNTR); |
| 99 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, INIT_PMCCNTR_CFG); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 100 | |
| 101 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 102 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 103 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), 0); |
| 104 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(i), 0); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 105 | } |
| 106 | #endif |
| 107 | } |
| 108 | |
| 109 | void ethosu_pmu_driver_exit(void) {} |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 110 | |
| 111 | void ETHOSU_PMU_Enable(void) |
| 112 | { |
| 113 | struct pmcr_r pmcr; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 114 | pmcr.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 115 | pmcr.cnt_en = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 116 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | void ETHOSU_PMU_Disable(void) |
| 120 | { |
| 121 | struct pmcr_r pmcr; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 122 | pmcr.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 123 | pmcr.cnt_en = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 124 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type) |
| 128 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 129 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num), pmu_event_value(type)); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num) |
| 133 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 134 | return pmu_event_type(ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num))); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | void ETHOSU_PMU_CYCCNT_Reset(void) |
| 138 | { |
| 139 | struct pmcr_r pmcr; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 140 | pmcr.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 141 | pmcr.cycle_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 142 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | void ETHOSU_PMU_EVCNTR_ALL_Reset(void) |
| 146 | { |
| 147 | struct pmcr_r pmcr; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 148 | pmcr.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 149 | pmcr.event_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 150 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | void ETHOSU_PMU_CNTR_Enable(uint32_t mask) |
| 154 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 155 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | void ETHOSU_PMU_CNTR_Disable(uint32_t mask) |
| 159 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 160 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 161 | } |
| 162 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 163 | uint32_t ETHOSU_PMU_CNTR_Status(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 164 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 165 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | uint64_t ETHOSU_PMU_Get_CCNTR(void) |
| 169 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 170 | uint64_t val1 = (((uint64_t)ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) | |
| 171 | ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); |
| 172 | uint64_t val2 = (((uint64_t)ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) | |
| 173 | ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 174 | |
| 175 | if (val2 > val1) |
| 176 | { |
| 177 | return val2; |
| 178 | } |
| 179 | return val1; |
| 180 | } |
| 181 | |
| 182 | void ETHOSU_PMU_Set_CCNTR(uint64_t val) |
| 183 | { |
| 184 | uint32_t mask = ETHOSU_PMU_CNTR_Status(); |
| 185 | |
| 186 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 187 | { |
| 188 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 189 | } |
| 190 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 191 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 192 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 193 | |
| 194 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 195 | { |
| 196 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num) |
| 201 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 202 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num)); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val) |
| 206 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 207 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num), val); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(void) |
| 211 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 212 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMOVSSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | // TODO: check if this function name match with the description & |
| 216 | // implementation. |
| 217 | void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask) |
| 218 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 219 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
| 223 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 224 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
| 228 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 229 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 230 | } |
| 231 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 232 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 233 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 234 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 235 | } |
| 236 | |
| 237 | void ETHOSU_PMU_CNTR_Increment(uint32_t mask) |
| 238 | { |
| 239 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(); |
| 240 | |
| 241 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 242 | { |
| 243 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 244 | { |
| 245 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 246 | uint64_t val = ETHOSU_PMU_Get_CCNTR() + 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 247 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 248 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 249 | if (cntrs_active & ETHOSU_PMU_CCNT_Msk) |
| 250 | { |
| 251 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 252 | } |
| 253 | } |
| 254 | } |
| 255 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 256 | { |
| 257 | uint32_t cntr = (0x0001 << i); |
| 258 | |
| 259 | if (mask & cntr) |
| 260 | { |
| 261 | ETHOSU_PMU_CNTR_Disable(cntr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 262 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i)); |
| 263 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), val + 1); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 264 | if (cntrs_active & cntr) |
| 265 | { |
| 266 | ETHOSU_PMU_CNTR_Enable(cntr); |
| 267 | } |
| 268 | } |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event) |
| 273 | { |
| 274 | struct pmccntr_cfg_r cfg; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 275 | cfg.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 276 | cfg.CYCLE_CNT_CFG_START = start_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 277 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event) |
| 281 | { |
| 282 | struct pmccntr_cfg_r cfg; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 283 | cfg.word = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 284 | cfg.CYCLE_CNT_CFG_STOP = stop_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame^] | 285 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 286 | } |