Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 18 | #include "ethosu_device.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 19 | #include "ethosu_common.h" |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 20 | #include "ethosu_config.h" |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 21 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 22 | #include <assert.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 23 | #include <stddef.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include <stdio.h> |
| 25 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #define BASEP_OFFSET 4 |
| 27 | #define REG_OFFSET 4 |
| 28 | #define BYTES_1KB 1024 |
| 29 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 30 | #define ADDRESS_BITS 48 |
| 31 | #define ADDRESS_MASK ((1ull << ADDRESS_BITS) - 1) |
| 32 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 33 | #if defined(ARM_NPU_STUB) |
| 34 | static uint32_t stream_length = 0; |
| 35 | #endif |
| 36 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 37 | enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, const void *base_address) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 38 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 39 | #if !defined(ARM_NPU_STUB) |
| 40 | dev->base_address = (uintptr_t)base_address; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 41 | ethosu_save_pmu_config(dev); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 42 | #else |
| 43 | UNUSED(dev); |
| 44 | UNUSED(base_address); |
| 45 | #endif |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 46 | return ETHOSU_SUCCESS; |
| 47 | } |
| 48 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 49 | enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 50 | { |
| 51 | struct id_r _id; |
| 52 | |
| 53 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 54 | _id.word = ethosu_read_reg(dev, NPU_REG_ID); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 55 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 56 | UNUSED(dev); |
| 57 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 58 | _id.word = 0; |
| 59 | _id.arch_patch_rev = NNX_ARCH_VERSION_PATCH; |
| 60 | _id.arch_minor_rev = NNX_ARCH_VERSION_MINOR; |
| 61 | _id.arch_major_rev = NNX_ARCH_VERSION_MAJOR; |
| 62 | #endif |
| 63 | |
| 64 | id->version_status = _id.version_status; |
| 65 | id->version_minor = _id.version_minor; |
| 66 | id->version_major = _id.version_major; |
| 67 | id->product_major = _id.product_major; |
| 68 | id->arch_patch_rev = _id.arch_patch_rev; |
| 69 | id->arch_minor_rev = _id.arch_minor_rev; |
| 70 | id->arch_major_rev = _id.arch_major_rev; |
| 71 | |
| 72 | return ETHOSU_SUCCESS; |
| 73 | } |
| 74 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 75 | enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 76 | { |
| 77 | struct config_r cfg = {.word = 0}; |
| 78 | |
| 79 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 80 | cfg.word = ethosu_read_reg(dev, NPU_REG_CONFIG); |
| 81 | #else |
| 82 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 83 | #endif |
| 84 | |
| 85 | config->macs_per_cc = cfg.macs_per_cc; |
| 86 | config->cmd_stream_version = cfg.cmd_stream_version; |
| 87 | config->shram_size = cfg.shram_size; |
| 88 | |
| 89 | return ETHOSU_SUCCESS; |
| 90 | } |
| 91 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 92 | enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev, |
| 93 | const uint8_t *cmd_stream_ptr, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 94 | uint32_t cms_length, |
| 95 | const uint64_t *base_addr, |
| 96 | int num_base_addr) |
| 97 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 98 | enum ethosu_error_codes ret_code = ETHOSU_SUCCESS; |
| 99 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 100 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 101 | ASSERT(num_base_addr <= ETHOSU_DRIVER_BASEP_INDEXES); |
| 102 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 103 | uint64_t qbase = (uint64_t)cmd_stream_ptr + BASE_POINTER_OFFSET; |
| 104 | ASSERT(qbase <= ADDRESS_MASK); |
| 105 | LOG_DEBUG("QBASE=0x%016llx, QSIZE=%u, base_pointer_offset=0x%08x\n", qbase, cms_length, BASE_POINTER_OFFSET); |
| 106 | ethosu_write_reg(dev, NPU_REG_QBASE0, qbase & 0xffffffff); |
| 107 | ethosu_write_reg(dev, NPU_REG_QBASE1, qbase >> 32); |
| 108 | ethosu_write_reg(dev, NPU_REG_QSIZE, cms_length); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 109 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 110 | for (int i = 0; i < num_base_addr; i++) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 111 | { |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 112 | uint64_t addr = base_addr[i] + BASE_POINTER_OFFSET; |
| 113 | ASSERT(addr <= ADDRESS_MASK); |
| 114 | LOG_DEBUG("BASEP%d=0x%016llx\n", i, addr); |
| 115 | ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i) * BASEP_OFFSET, addr & 0xffffffff); |
| 116 | ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i + 1) * BASEP_OFFSET, addr >> 32); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 117 | } |
| 118 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 119 | ret_code = ethosu_set_command_run(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 120 | #else |
| 121 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 122 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 123 | stream_length = cms_length; |
| 124 | UNUSED(cmd_stream_ptr); |
| 125 | UNUSED(base_addr); |
| 126 | ASSERT(num_base_addr < ETHOSU_DRIVER_BASEP_INDEXES); |
| 127 | #if defined(NDEBUG) |
| 128 | UNUSED(num_base_addr); |
| 129 | #endif |
| 130 | #endif |
| 131 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 132 | return ret_code; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 133 | } |
| 134 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 135 | enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_raised) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 136 | { |
| 137 | #if !defined(ARM_NPU_STUB) |
| 138 | struct status_r status; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 139 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 140 | if (status.irq_raised == 1) |
| 141 | { |
| 142 | *irq_raised = 1; |
| 143 | } |
| 144 | else |
| 145 | { |
| 146 | *irq_raised = 0; |
| 147 | } |
| 148 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 149 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 150 | *irq_raised = 1; |
| 151 | #endif |
| 152 | return ETHOSU_SUCCESS; |
| 153 | } |
| 154 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 155 | enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 156 | { |
| 157 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 158 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 159 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 160 | struct cmd_r cmd; |
Per Ã…strand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 161 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 162 | cmd.word = 0; |
| 163 | cmd.clear_irq = 1; |
| 164 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 165 | cmd.power_q_enable = oldcmd.power_q_enable; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 166 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 167 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 168 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 169 | #endif |
| 170 | return ETHOSU_SUCCESS; |
| 171 | } |
| 172 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 173 | // TODO Understand settings of privilege/security level and update API. |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 174 | enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 175 | { |
| 176 | enum ethosu_error_codes return_code = ETHOSU_SUCCESS; |
| 177 | #if !defined(ARM_NPU_STUB) |
| 178 | struct reset_r reset; |
| 179 | struct prot_r prot; |
| 180 | |
| 181 | reset.word = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 182 | reset.pending_CPL = PRIVILEGE_LEVEL_USER; // TODO, how to get the host privilege level |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 183 | reset.pending_CSL = SECURITY_LEVEL_NON_SECURE; // TODO, how to get Security level |
| 184 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 185 | prot.word = ethosu_read_reg(dev, NPU_REG_PROT); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 186 | |
| 187 | if (prot.active_CPL < reset.pending_CPL && prot.active_CSL > reset.pending_CSL) |
| 188 | { |
| 189 | // Register access not permitted |
| 190 | return ETHOSU_GENERIC_FAILURE; |
| 191 | } |
| 192 | // Reset and set security level |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 193 | ethosu_write_reg(dev, NPU_REG_RESET, reset.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 194 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 195 | return_code = ethosu_wait_for_reset(dev); |
| 196 | #else |
| 197 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 198 | #endif |
| 199 | |
| 200 | return return_code; |
| 201 | } |
| 202 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 203 | enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 204 | { |
| 205 | #if !defined(ARM_NPU_STUB) |
| 206 | struct status_r status; |
| 207 | |
| 208 | // Wait until reset status indicates that reset has been completed |
| 209 | for (int i = 0; i < 100000; i++) |
| 210 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 211 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 212 | if (0 == status.reset_status) |
| 213 | { |
| 214 | break; |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | if (1 == status.reset_status) |
| 219 | { |
| 220 | return ETHOSU_GENERIC_FAILURE; |
| 221 | } |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 222 | #else |
| 223 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 224 | #endif |
| 225 | |
| 226 | return ETHOSU_SUCCESS; |
| 227 | } |
| 228 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 229 | enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev, |
| 230 | uint32_t start_address, |
| 231 | uint16_t num_reg, |
| 232 | uint32_t *reg) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 233 | { |
| 234 | #if !defined(ARM_NPU_STUB) |
| 235 | uint32_t address = start_address; |
| 236 | |
Douglas Troha | 2e7e3b7 | 2020-05-14 20:28:31 +0200 | [diff] [blame] | 237 | ASSERT((start_address + num_reg) < ID_REGISTERS_SIZE); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 238 | |
| 239 | for (int i = 0; i < num_reg; i++) |
| 240 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 241 | reg[i] = ethosu_read_reg(dev, address); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 242 | address += REG_OFFSET; |
| 243 | } |
| 244 | #else |
| 245 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 246 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 247 | UNUSED(start_address); |
| 248 | UNUSED(num_reg); |
| 249 | UNUSED(reg); |
| 250 | #endif |
| 251 | |
| 252 | return ETHOSU_SUCCESS; |
| 253 | } |
| 254 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 255 | enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 256 | { |
| 257 | if (memory_type > ETHOSU_AXI1_OUTSTANDING_COUNTER3) |
| 258 | { |
| 259 | return ETHOSU_INVALID_PARAM; |
| 260 | } |
| 261 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 262 | ethosu_write_reg(dev, NPU_REG_QCONFIG, memory_type); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 263 | #else |
| 264 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 265 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 266 | UNUSED(memory_type); |
| 267 | #endif |
| 268 | return ETHOSU_SUCCESS; |
| 269 | } |
| 270 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 271 | enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev, |
| 272 | uint8_t region, |
| 273 | enum ethosu_memory_type memory_type) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 274 | { |
| 275 | if (region > 7) |
| 276 | { |
| 277 | return ETHOSU_INVALID_PARAM; |
| 278 | } |
| 279 | #if !defined(ARM_NPU_STUB) |
| 280 | struct regioncfg_r regioncfg; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 281 | regioncfg.word = ethosu_read_reg(dev, NPU_REG_REGIONCFG); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 282 | regioncfg.word &= ~(0x3 << (2 * region)); |
| 283 | regioncfg.word |= (memory_type & 0x3) << (2 * region); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 284 | ethosu_write_reg(dev, NPU_REG_REGIONCFG, regioncfg.word); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 285 | LOG_DEBUG("REGIONCFG%u=0x%08x\n", region, regioncfg.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 286 | #else |
| 287 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 288 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 289 | UNUSED(region); |
| 290 | UNUSED(memory_type); |
| 291 | #endif |
| 292 | return ETHOSU_SUCCESS; |
| 293 | } |
| 294 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 295 | enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev, |
| 296 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 297 | enum ethosu_axi_limit_mem_type memtype, |
| 298 | uint8_t max_reads, |
| 299 | uint8_t max_writes) |
| 300 | { |
| 301 | #if !defined(ARM_NPU_STUB) |
| 302 | struct axi_limit0_r axi_limit0; |
Per Ã…strand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 303 | axi_limit0.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 304 | axi_limit0.max_beats = max_beats; |
| 305 | axi_limit0.memtype = memtype; |
| 306 | axi_limit0.max_outstanding_read_m1 = max_reads - 1; |
| 307 | axi_limit0.max_outstanding_write_m1 = max_writes - 1; |
| 308 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 309 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT0, axi_limit0.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 310 | #else |
| 311 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 312 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 313 | UNUSED(max_beats); |
| 314 | UNUSED(memtype); |
| 315 | UNUSED(max_reads); |
| 316 | UNUSED(max_writes); |
| 317 | #endif |
| 318 | |
| 319 | return ETHOSU_SUCCESS; |
| 320 | } |
| 321 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 322 | enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev, |
| 323 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 324 | enum ethosu_axi_limit_mem_type memtype, |
| 325 | uint8_t max_reads, |
| 326 | uint8_t max_writes) |
| 327 | { |
| 328 | #if !defined(ARM_NPU_STUB) |
| 329 | struct axi_limit1_r axi_limit1; |
Per Ã…strand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 330 | axi_limit1.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 331 | axi_limit1.max_beats = max_beats; |
| 332 | axi_limit1.memtype = memtype; |
| 333 | axi_limit1.max_outstanding_read_m1 = max_reads - 1; |
| 334 | axi_limit1.max_outstanding_write_m1 = max_writes - 1; |
| 335 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 336 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT1, axi_limit1.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 337 | #else |
| 338 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 339 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 340 | UNUSED(max_beats); |
| 341 | UNUSED(memtype); |
| 342 | UNUSED(max_reads); |
| 343 | UNUSED(max_writes); |
| 344 | #endif |
| 345 | |
| 346 | return ETHOSU_SUCCESS; |
| 347 | } |
| 348 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 349 | enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev, |
| 350 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 351 | enum ethosu_axi_limit_mem_type memtype, |
| 352 | uint8_t max_reads, |
| 353 | uint8_t max_writes) |
| 354 | { |
| 355 | #if !defined(ARM_NPU_STUB) |
| 356 | struct axi_limit2_r axi_limit2; |
Per Ã…strand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 357 | axi_limit2.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 358 | axi_limit2.max_beats = max_beats; |
| 359 | axi_limit2.memtype = memtype; |
| 360 | axi_limit2.max_outstanding_read_m1 = max_reads - 1; |
| 361 | axi_limit2.max_outstanding_write_m1 = max_writes - 1; |
| 362 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 363 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT2, axi_limit2.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 364 | #else |
| 365 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 366 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 367 | UNUSED(max_beats); |
| 368 | UNUSED(memtype); |
| 369 | UNUSED(max_reads); |
| 370 | UNUSED(max_writes); |
| 371 | #endif |
| 372 | |
| 373 | return ETHOSU_SUCCESS; |
| 374 | } |
| 375 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 376 | enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev, |
| 377 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 378 | enum ethosu_axi_limit_mem_type memtype, |
| 379 | uint8_t max_reads, |
| 380 | uint8_t max_writes) |
| 381 | { |
| 382 | #if !defined(ARM_NPU_STUB) |
| 383 | struct axi_limit3_r axi_limit3; |
Per Ã…strand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 384 | axi_limit3.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 385 | axi_limit3.max_beats = max_beats; |
| 386 | axi_limit3.memtype = memtype; |
| 387 | axi_limit3.max_outstanding_read_m1 = max_reads - 1; |
| 388 | axi_limit3.max_outstanding_write_m1 = max_writes - 1; |
| 389 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 390 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT3, axi_limit3.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 391 | #else |
| 392 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 393 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 394 | UNUSED(max_beats); |
| 395 | UNUSED(memtype); |
| 396 | UNUSED(max_reads); |
| 397 | UNUSED(max_writes); |
| 398 | #endif |
| 399 | |
| 400 | return ETHOSU_SUCCESS; |
| 401 | } |
| 402 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 403 | enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 404 | { |
| 405 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 406 | *revision = ethosu_read_reg(dev, NPU_REG_REVISION); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 407 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 408 | UNUSED(dev); |
| 409 | *revision = 0xDEADC0DE; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 410 | #endif |
| 411 | return ETHOSU_SUCCESS; |
| 412 | } |
| 413 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 414 | enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 415 | { |
| 416 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 417 | *qread = ethosu_read_reg(dev, NPU_REG_QREAD); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 418 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 419 | UNUSED(dev); |
| 420 | *qread = stream_length; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 421 | #endif |
| 422 | return ETHOSU_SUCCESS; |
| 423 | } |
| 424 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 425 | enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 426 | { |
| 427 | #if !defined(ARM_NPU_STUB) |
| 428 | struct status_r status; |
| 429 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 430 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 431 | *status_mask = status.word & 0xFFFF; |
| 432 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 433 | UNUSED(dev); |
| 434 | *status_mask = 0x0000; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 435 | #endif |
| 436 | return ETHOSU_SUCCESS; |
| 437 | } |
| 438 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 439 | enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 440 | { |
| 441 | #if !defined(ARM_NPU_STUB) |
| 442 | struct status_r status; |
| 443 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 444 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 445 | *irq_history_mask = status.irq_history_mask; |
| 446 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 447 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 448 | *irq_history_mask = 0xffff; |
| 449 | #endif |
| 450 | return ETHOSU_SUCCESS; |
| 451 | } |
| 452 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 453 | enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 454 | { |
| 455 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 456 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 457 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 458 | |
| 459 | struct cmd_r cmd; |
| 460 | cmd.word = 0; |
| 461 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 462 | cmd.power_q_enable = oldcmd.power_q_enable; |
| 463 | cmd.clear_irq_history = irq_history_clear_mask; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 464 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 465 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 466 | UNUSED(dev); |
Bhavik Patel | bcb5aaa | 2020-05-12 10:09:41 +0200 | [diff] [blame] | 467 | UNUSED(irq_history_clear_mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 468 | #endif |
| 469 | return ETHOSU_SUCCESS; |
| 470 | } |
| 471 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 472 | enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 473 | { |
| 474 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 475 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 476 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 477 | |
| 478 | struct cmd_r cmd; |
| 479 | cmd.word = 0; |
| 480 | cmd.transition_to_running_state = 1; |
| 481 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 482 | cmd.power_q_enable = oldcmd.power_q_enable; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 483 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 484 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 485 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 486 | #endif |
| 487 | return ETHOSU_SUCCESS; |
| 488 | } |
| 489 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 490 | enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 491 | { |
| 492 | #if !defined(ARM_NPU_STUB) |
| 493 | int i = 0; |
| 494 | uint32_t address = NPU_REG_SHARED_BUFFER0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 495 | ethosu_write_reg(dev, NPU_REG_DEBUG_ADDRESS, section * BYTES_1KB); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 496 | |
| 497 | while (address <= NPU_REG_SHARED_BUFFER255) |
| 498 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 499 | shram_p[i] = ethosu_read_reg(dev, address); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 500 | address += REG_OFFSET; |
| 501 | i++; |
| 502 | } |
| 503 | #else |
| 504 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 505 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 506 | UNUSED(section); |
| 507 | UNUSED(shram_p); |
| 508 | #endif |
| 509 | |
| 510 | return ETHOSU_SUCCESS; |
| 511 | } |
| 512 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 513 | enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev, |
| 514 | enum ethosu_clock_q_request clock_q, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 515 | enum ethosu_power_q_request power_q) |
| 516 | { |
| 517 | #if !defined(ARM_NPU_STUB) |
| 518 | struct cmd_r cmd; |
| 519 | cmd.word = 0; |
| 520 | cmd.clock_q_enable = clock_q; |
| 521 | cmd.power_q_enable = power_q; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 522 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 523 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 524 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 525 | UNUSED(clock_q); |
| 526 | UNUSED(power_q); |
| 527 | #endif |
| 528 | return ETHOSU_SUCCESS; |
| 529 | } |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 530 | |
| 531 | uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address) |
| 532 | { |
| 533 | #if !defined(ARM_NPU_STUB) |
| 534 | ASSERT(dev->base_address != NULL); |
| 535 | |
| 536 | volatile uint32_t *reg = (uint32_t *)(uintptr_t)(dev->base_address + address); |
| 537 | return *reg; |
| 538 | #else |
| 539 | UNUSED(dev); |
| 540 | UNUSED(address); |
| 541 | |
| 542 | return 0; |
| 543 | #endif |
| 544 | } |
| 545 | |
| 546 | void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value) |
| 547 | { |
| 548 | #if !defined(ARM_NPU_STUB) |
| 549 | ASSERT(dev->base_address != NULL); |
| 550 | |
| 551 | volatile uint32_t *reg = (uint32_t *)(uintptr_t)(dev->base_address + address); |
| 552 | *reg = value; |
| 553 | #else |
| 554 | UNUSED(dev); |
| 555 | UNUSED(address); |
| 556 | UNUSED(value); |
| 557 | #endif |
| 558 | } |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 559 | |
| 560 | enum ethosu_error_codes ethosu_save_pmu_config(struct ethosu_device *dev) |
| 561 | { |
| 562 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 563 | // Save the PMU control register |
| 564 | dev->pmcr = ethosu_read_reg(dev, NPU_REG_PMCR); |
| 565 | |
| 566 | // Save IRQ control |
| 567 | dev->pmint = ethosu_read_reg(dev, NPU_REG_PMINTSET); |
| 568 | |
| 569 | // Save the enabled events mask |
| 570 | dev->pmcnten = ethosu_read_reg(dev, NPU_REG_PMCNTENSET); |
| 571 | |
| 572 | // Save start and stop event |
| 573 | dev->pmccntr_cfg = ethosu_read_reg(dev, NPU_REG_PMCCNTR_CFG); |
| 574 | |
| 575 | // Save the cycle counter |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 576 | dev->pmccntr = ETHOSU_PMU_Get_CCNTR(); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 577 | |
| 578 | // Save the event settings and counters |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 579 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 580 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 581 | dev->pmu_evcntr[i] = ethosu_read_reg(dev, NPU_REG_PMEVCNTR0 + i * sizeof(uint32_t)); |
| 582 | dev->pmu_evtypr[i] = ethosu_read_reg(dev, NPU_REG_PMEVTYPER0 + i * sizeof(uint32_t)); |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 583 | } |
| 584 | #else |
| 585 | UNUSED(dev); |
| 586 | #endif |
| 587 | |
| 588 | return ETHOSU_SUCCESS; |
| 589 | } |
| 590 | |
| 591 | enum ethosu_error_codes ethosu_restore_pmu_config(struct ethosu_device *dev) |
| 592 | { |
| 593 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 594 | // Restore PMU control register |
| 595 | ethosu_write_reg(dev, NPU_REG_PMCR, dev->pmcr); |
| 596 | |
| 597 | // Restore IRQ control |
| 598 | ethosu_write_reg(dev, NPU_REG_PMINTSET, dev->pmint); |
| 599 | |
| 600 | // Restore enabled event mask |
| 601 | ethosu_write_reg(dev, NPU_REG_PMCNTENSET, dev->pmcnten); |
| 602 | |
| 603 | // Restore start and stop event |
| 604 | ethosu_write_reg(dev, NPU_REG_PMCCNTR_CFG, dev->pmccntr_cfg); |
| 605 | |
| 606 | // Restore the cycle counter |
| 607 | ETHOSU_PMU_Set_CCNTR(dev->pmccntr); |
| 608 | |
| 609 | // Restore event settings and counters |
| 610 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 611 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 612 | ethosu_write_reg(dev, NPU_REG_PMEVCNTR0 + i * sizeof(uint32_t), dev->pmu_evcntr[i]); |
| 613 | ethosu_write_reg(dev, NPU_REG_PMEVTYPER0 + i * sizeof(uint32_t), dev->pmu_evtypr[i]); |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 614 | } |
| 615 | #else |
| 616 | UNUSED(dev); |
| 617 | #endif |
| 618 | |
| 619 | return ETHOSU_SUCCESS; |
| 620 | } |