Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2009-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /* |
| 20 | *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- |
| 21 | */ |
| 22 | |
| 23 | /*---------------------- ITCM Configuration ---------------------------------- |
| 24 | <h> Flash Configuration |
| 25 | <o0> Flash Base Address <0x0-0xFFFFFFFF:8> |
| 26 | <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 27 | </h> |
| 28 | -----------------------------------------------------------------------------*/ |
| 29 | __ROM_BASE = 0x00000000; |
| 30 | __ROM_SIZE = 0x00080000; |
| 31 | |
| 32 | /*--------------------- DTCM RAM Configuration ---------------------------- |
| 33 | <h> RAM Configuration |
| 34 | <o0> RAM Base Address <0x0-0xFFFFFFFF:8> |
| 35 | <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 36 | </h> |
| 37 | -----------------------------------------------------------------------------*/ |
| 38 | __RAM_BASE = 0x20000000; |
| 39 | __RAM_SIZE = 0x00080000; |
| 40 | |
| 41 | /*--------------------- Embedded SRAM Configuration ---------------------------- |
| 42 | <h> SRAM Configuration |
| 43 | <o0> SRAM Base Address <0x0-0xFFFFFFFF:8> |
| 44 | <o1> SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 45 | </h> |
| 46 | -----------------------------------------------------------------------------*/ |
| 47 | __SRAM_BASE = 0x21000000; |
| 48 | __SRAM_SIZE = 0x00200000; |
| 49 | |
| 50 | /*--------------------- Stack / Heap Configuration ---------------------------- |
| 51 | <h> Stack / Heap Configuration |
| 52 | <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 53 | <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 54 | </h> |
| 55 | -----------------------------------------------------------------------------*/ |
| 56 | __STACK_SIZE = 0x00008000; |
| 57 | __HEAP_SIZE = 0x00008000; |
| 58 | |
| 59 | /*--------------------- Embedded RAM Configuration ---------------------------- |
| 60 | <h> DDR Configuration |
| 61 | <o0> DDR Base Address <0x0-0xFFFFFFFF:8> |
| 62 | <o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| 63 | </h> |
| 64 | -----------------------------------------------------------------------------*/ |
| 65 | __DDR_BASE = 0x60000000; |
| 66 | __DDR_SIZE = 0x02000000; |
| 67 | |
| 68 | /* |
| 69 | *-------------------- <<< end of configuration section >>> ------------------- |
| 70 | */ |
| 71 | |
| 72 | MEMORY |
| 73 | { |
| 74 | ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE |
| 75 | DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE |
| 76 | SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE |
| 77 | DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE |
| 78 | } |
| 79 | |
| 80 | /* Linker script to place sections and symbol values. Should be used together |
| 81 | * with other linker script that defines memory regions ITCM and RAM. |
| 82 | * It references following symbols, which must be defined in code: |
| 83 | * Reset_Handler : Entry of reset handler |
| 84 | * |
| 85 | * It defines following symbols, which code can use without definition: |
| 86 | * __exidx_start |
| 87 | * __exidx_end |
| 88 | * __copy_table_start__ |
| 89 | * __copy_table_end__ |
| 90 | * __zero_table_start__ |
| 91 | * __zero_table_end__ |
| 92 | * __etext |
| 93 | * __data_start__ |
| 94 | * __preinit_array_start |
| 95 | * __preinit_array_end |
| 96 | * __init_array_start |
| 97 | * __init_array_end |
| 98 | * __fini_array_start |
| 99 | * __fini_array_end |
| 100 | * __data_end__ |
| 101 | * __bss_start__ |
| 102 | * __bss_end__ |
| 103 | * __end__ |
| 104 | * end |
| 105 | * __HeapLimit |
| 106 | * __StackLimit |
| 107 | * __StackTop |
| 108 | * __stack |
| 109 | */ |
| 110 | ENTRY(Reset_Handler) |
| 111 | |
| 112 | SECTIONS |
| 113 | { |
| 114 | .text : |
| 115 | { |
| 116 | KEEP(*(.vectors)) |
| 117 | *(.text*) |
| 118 | |
| 119 | KEEP(*(.init)) |
| 120 | KEEP(*(.fini)) |
| 121 | |
| 122 | /* .ctors */ |
| 123 | *crtbegin.o(.ctors) |
| 124 | *crtbegin?.o(.ctors) |
| 125 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 126 | *(SORT(.ctors.*)) |
| 127 | *(.ctors) |
| 128 | |
| 129 | /* .dtors */ |
| 130 | *crtbegin.o(.dtors) |
| 131 | *crtbegin?.o(.dtors) |
| 132 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 133 | *(SORT(.dtors.*)) |
| 134 | *(.dtors) |
| 135 | |
| 136 | *(.rodata*) |
| 137 | |
| 138 | KEEP(*(.eh_frame*)) |
| 139 | } > ITCM |
| 140 | |
| 141 | /* |
| 142 | * SG veneers: |
| 143 | * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address |
| 144 | * must be set, either with the command line option �--section-start� or in a linker script, |
| 145 | * to indicate where to place these veneers in memory. |
| 146 | */ |
| 147 | /* |
| 148 | .gnu.sgstubs : |
| 149 | { |
| 150 | . = ALIGN(32); |
| 151 | } > ITCM |
| 152 | */ |
| 153 | .ARM.extab : |
| 154 | { |
| 155 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
| 156 | } > ITCM |
| 157 | |
| 158 | __exidx_start = .; |
| 159 | .ARM.exidx : |
| 160 | { |
| 161 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| 162 | } > ITCM |
| 163 | __exidx_end = .; |
| 164 | |
| 165 | .copy.table : |
| 166 | { |
| 167 | . = ALIGN(4); |
| 168 | __copy_table_start__ = .; |
| 169 | LONG (__etext) |
| 170 | LONG (__data_start__) |
| 171 | LONG (__data_end__ - __data_start__) |
| 172 | /* Add each additional data section here */ |
| 173 | __copy_table_end__ = .; |
| 174 | } > ITCM |
| 175 | |
| 176 | .zero.table : |
| 177 | { |
| 178 | . = ALIGN(4); |
| 179 | __zero_table_start__ = .; |
| 180 | /* Add each additional bss section here */ |
| 181 | /* |
| 182 | LONG (__bss2_start__) |
| 183 | LONG (__bss2_end__ - __bss2_start__) |
| 184 | */ |
| 185 | __zero_table_end__ = .; |
| 186 | } > ITCM |
| 187 | |
| 188 | /** |
| 189 | * Location counter can end up 2byte aligned with narrow Thumb code but |
| 190 | * __etext is assumed by startup code to be the LMA of a section in DTCM |
| 191 | * which must be 4byte aligned |
| 192 | */ |
| 193 | __etext = ALIGN (4); |
| 194 | |
| 195 | .data : AT (__etext) |
| 196 | { |
| 197 | __data_start__ = .; |
| 198 | *(vtable) |
| 199 | *(.data) |
| 200 | *(.data.*) |
| 201 | |
| 202 | . = ALIGN(4); |
| 203 | /* preinit data */ |
| 204 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 205 | KEEP(*(.preinit_array)) |
| 206 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 207 | |
| 208 | . = ALIGN(4); |
| 209 | /* init data */ |
| 210 | PROVIDE_HIDDEN (__init_array_start = .); |
| 211 | KEEP(*(SORT(.init_array.*))) |
| 212 | KEEP(*(.init_array)) |
| 213 | PROVIDE_HIDDEN (__init_array_end = .); |
| 214 | |
| 215 | |
| 216 | . = ALIGN(4); |
| 217 | /* finit data */ |
| 218 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 219 | KEEP(*(SORT(.fini_array.*))) |
| 220 | KEEP(*(.fini_array)) |
| 221 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 222 | |
| 223 | KEEP(*(.jcr*)) |
| 224 | . = ALIGN(4); |
| 225 | /* All data end */ |
| 226 | __data_end__ = .; |
| 227 | |
| 228 | } > DTCM |
| 229 | |
| 230 | /* |
| 231 | * Secondary data section, optional |
| 232 | * |
| 233 | * Remember to add each additional data section |
| 234 | * to the .copy.table above to asure proper |
| 235 | * initialization during startup. |
| 236 | */ |
| 237 | /* |
| 238 | __etext2 = ALIGN (4); |
| 239 | |
| 240 | .data2 : AT (__etext2) |
| 241 | { |
| 242 | . = ALIGN(4); |
| 243 | __data2_start__ = .; |
| 244 | *(.data2) |
| 245 | *(.data2.*) |
| 246 | . = ALIGN(4); |
| 247 | __data2_end__ = .; |
| 248 | |
| 249 | } > RAM2 |
| 250 | */ |
| 251 | |
| 252 | #ifndef ETHOSU_FAST_MEMORY_SIZE |
| 253 | .sram : |
| 254 | { |
| 255 | . = ALIGN(16); |
| 256 | *(.bss.NoInit) |
| 257 | . = ALIGN(16); |
| 258 | } > SRAM AT > SRAM |
| 259 | #else |
| 260 | .sram : |
| 261 | { |
| 262 | . = ALIGN(16); |
| 263 | *(.bss.ethosu_fast_memory); |
| 264 | . = ALIGN(16); |
| 265 | } > SRAM AT > SRAM |
| 266 | |
| 267 | .bss.NoInit : |
| 268 | { |
| 269 | . = ALIGN(16); |
| 270 | *(.bss.NoInit) |
| 271 | . = ALIGN(16); |
| 272 | } > DDR AT > DDR |
| 273 | #endif |
| 274 | |
| 275 | .bss : |
| 276 | { |
| 277 | . = ALIGN(4); |
| 278 | __bss_start__ = .; |
| 279 | *(.bss) |
| 280 | *(.bss.*) |
| 281 | *(COMMON) |
| 282 | . = ALIGN(4); |
| 283 | __bss_end__ = .; |
| 284 | } > DTCM AT > DTCM |
| 285 | |
| 286 | |
| 287 | /* |
| 288 | * Secondary bss section, optional |
| 289 | * |
| 290 | * Remember to add each additional bss section |
| 291 | * to the .zero.table above to asure proper |
| 292 | * initialization during startup. |
| 293 | */ |
| 294 | /* |
| 295 | .bss2 : |
| 296 | { |
| 297 | . = ALIGN(4); |
| 298 | __bss2_start__ = .; |
| 299 | *(.bss2) |
| 300 | *(.bss2.*) |
| 301 | . = ALIGN(4); |
| 302 | __bss2_end__ = .; |
| 303 | } > RAM2 AT > RAM2 |
| 304 | */ |
| 305 | |
| 306 | .ddr : |
| 307 | { |
| 308 | /* __attribute__((aligned(16))) is not handled by the cmsis startup code. |
| 309 | * Force the alignement here as a workaround */ |
| 310 | . = ALIGN(4); |
| 311 | *(input_data_sec) |
| 312 | . = ALIGN(16); |
| 313 | *(network_model_sec) |
| 314 | *(expected_output_data_sec) |
| 315 | . = ALIGN (16); |
| 316 | } > DDR |
| 317 | |
| 318 | .heap (COPY) : |
| 319 | { |
| 320 | . = ALIGN(8); |
| 321 | __end__ = .; |
| 322 | PROVIDE(end = .); |
| 323 | . = . + __HEAP_SIZE; |
| 324 | . = ALIGN(8); |
| 325 | __HeapLimit = .; |
| 326 | } > DTCM |
| 327 | |
| 328 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 329 | { |
| 330 | . = ALIGN(8); |
| 331 | __StackLimit = .; |
| 332 | . = . + __STACK_SIZE; |
| 333 | . = ALIGN(8); |
| 334 | __StackTop = .; |
| 335 | } > DTCM |
| 336 | PROVIDE(__stack = __StackTop); |
| 337 | |
| 338 | /* Check if data + heap + stack exceeds DTCM limit */ |
| 339 | ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack") |
| 340 | } |