Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame^] | 1 | #! cpp |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 5 | * |
| 6 | * SPDX-License-Identifier: Apache-2.0 |
| 7 | * |
| 8 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 9 | * not use this file except in compliance with the License. |
| 10 | * You may obtain a copy of the License at |
| 11 | * |
| 12 | * www.apache.org/licenses/LICENSE-2.0 |
| 13 | * |
| 14 | * Unless required by applicable law or agreed to in writing, software |
| 15 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 16 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 17 | * See the License for the specific language governing permissions and |
| 18 | * limitations under the License. |
| 19 | */ |
| 20 | |
| 21 | #ifndef STACK_SIZE |
| 22 | #define STACK_SIZE 0x8000 |
| 23 | #endif |
| 24 | |
| 25 | #ifndef HEAP_SIZE |
| 26 | #define HEAP_SIZE 0x8000 |
| 27 | #endif |
| 28 | |
| 29 | APP_IMAGE 0x00000000 0x01000000 |
| 30 | { |
| 31 | ; ITCM 512kB |
| 32 | rom_exec 0x00000000 0x00080000 |
| 33 | { |
| 34 | *.o (RESET, +First) |
| 35 | *(InRoot$$Sections) |
| 36 | .ANY (+RO) |
| 37 | } |
| 38 | |
| 39 | ; Shared between Cortex-M and the NPU |
| 40 | DATA_SRAM 0x01000000 UNINIT 0x00200000 {} |
| 41 | |
| 42 | ; SSE-300 SRAM (3 cycles read latency) from M55/U55 |
| 43 | ; 2x2MB - only first part mapped |
| 44 | SRAM 0x21000000 UNINIT 0x00200000 |
| 45 | { |
| 46 | #ifndef ETHOSU_FAST_MEMORY_SIZE |
| 47 | ; Place tensor arena in SRAM if we do not have a fast memory area |
| 48 | * (.bss.NoInit) ; Tensor Arena |
| 49 | #else |
| 50 | * (.bss.ethosu_scratch) |
| 51 | #endif |
| 52 | } |
| 53 | |
| 54 | ; DTCM 512kB |
| 55 | ; Only accessible from the Cortex-M |
| 56 | DTCM 0x20000000 (0x00080000 - STACK_SIZE - HEAP_SIZE) |
| 57 | { |
| 58 | .ANY (+RW +ZI) |
| 59 | } |
| 60 | |
| 61 | ARM_LIB_HEAP (0x20080000 - STACK_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} |
| 62 | ARM_LIB_STACK (0x20080000 - STACK_SIZE) EMPTY ALIGN 8 STACK_SIZE {} |
| 63 | } |
| 64 | |
| 65 | LOAD_REGION_1 0x60000000 0x02000000 |
| 66 | { |
| 67 | ; 2GB DDR4 available |
| 68 | rom_dram 0x60000000 0x02000000 |
| 69 | { |
| 70 | * (network_model_sec) |
| 71 | * (input_data_sec) |
| 72 | * (expected_output_data_sec) |
| 73 | } |
| 74 | |
| 75 | #ifdef ETHOSU_FAST_MEMORY_SIZE |
| 76 | ; Place tensor arena in DRAM if we have a fast memory area |
| 77 | ARENA +0 UNINIT ALIGN 16 |
| 78 | { |
| 79 | * (.bss.NoInit) ; Tensor Arena |
| 80 | } |
| 81 | #endif |
| 82 | } |