Default timing adapters mode value
Setting default value for the timing adapters mode register.
Change-Id: I71efd96b8235d476a0d133c4f93cb97530172ab5
diff --git a/targets/corstone-300/CMakeLists.txt b/targets/corstone-300/CMakeLists.txt
index 12902d3..6558e0d 100644
--- a/targets/corstone-300/CMakeLists.txt
+++ b/targets/corstone-300/CMakeLists.txt
@@ -103,7 +103,10 @@
foreach(index RANGE 0 1)
set(name ETHOSU_TA_${register}_${index})
set(${name} -1 CACHE STRING "${name}")
- target_compile_definitions(ethosu_target_common INTERFACE ${name}=${${name}})
+
+ if (${name} GREATER_EQUAL 0)
+ target_compile_definitions(ethosu_target_common INTERFACE ${name}=${${name}})
+ endif()
endforeach()
endforeach()
diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp
index b780c09..f979f85 100644
--- a/targets/corstone-300/target.cpp
+++ b/targets/corstone-300/target.cpp
@@ -67,83 +67,107 @@
* Timing Adapters
****************************************************************************/
-#if ETHOSU_TA_MAXR_0 < 0
+#ifndef ETHOSU_TA_MAXR_0
#define ETHOSU_TA_MAXR_0 0
#endif
-#if ETHOSU_TA_MAXW_0 < 0
+
+#ifndef ETHOSU_TA_MAXW_0
#define ETHOSU_TA_MAXW_0 0
#endif
-#if ETHOSU_TA_MAXRW_0 < 0
+
+#ifndef ETHOSU_TA_MAXRW_0
#define ETHOSU_TA_MAXRW_0 0
#endif
-#if ETHOSU_TA_RLATENCY_0 < 0
+
+#ifndef ETHOSU_TA_RLATENCY_0
#define ETHOSU_TA_RLATENCY_0 0
#endif
-#if ETHOSU_TA_WLATENCY_0 < 0
+
+#ifndef ETHOSU_TA_WLATENCY_0
#define ETHOSU_TA_WLATENCY_0 0
#endif
-#if ETHOSU_TA_PULSE_ON_0 < 0
+
+#ifndef ETHOSU_TA_PULSE_ON_0
#define ETHOSU_TA_PULSE_ON_0 0
#endif
-#if ETHOSU_TA_PULSE_OFF_0 < 0
+
+#ifndef ETHOSU_TA_PULSE_OFF_0
#define ETHOSU_TA_PULSE_OFF_0 0
#endif
-#if ETHOSU_TA_BWCAP_0 < 0
+
+#ifndef ETHOSU_TA_BWCAP_0
#define ETHOSU_TA_BWCAP_0 0
#endif
-#if ETHOSU_TA_PERFCTRL_0 < 0
+
+#ifndef ETHOSU_TA_PERFCTRL_0
#define ETHOSU_TA_PERFCTRL_0 0
#endif
-#if ETHOSU_TA_PERFCNT_0 < 0
+
+#ifndef ETHOSU_TA_PERFCNT_0
#define ETHOSU_TA_PERFCNT_0 0
#endif
-#if ETHOSU_TA_MODE_0 < 0
-#define ETHOSU_TA_MODE_0 0
+
+#ifndef ETHOSU_TA_MODE_0
+#define ETHOSU_TA_MODE_0 1
#endif
-#if ETHOSU_TA_HISTBIN_0 < 0
+
+#ifndef ETHOSU_TA_HISTBIN_0
#define ETHOSU_TA_HISTBIN_0 0
#endif
-#if ETHOSU_TA_HISTCNT_0 < 0
+
+#ifndef ETHOSU_TA_HISTCNT_0
#define ETHOSU_TA_HISTCNT_0 0
#endif
-#if ETHOSU_TA_MAXR_1 < 0
+#ifndef ETHOSU_TA_MAXR_1
#define ETHOSU_TA_MAXR_1 0
#endif
-#if ETHOSU_TA_MAXW_1 < 0
+
+#ifndef ETHOSU_TA_MAXW_1
#define ETHOSU_TA_MAXW_1 0
#endif
-#if ETHOSU_TA_MAXRW_1 < 0
+
+#ifndef ETHOSU_TA_MAXRW_1
#define ETHOSU_TA_MAXRW_1 0
#endif
-#if ETHOSU_TA_RLATENCY_1 < 0
+
+#ifndef ETHOSU_TA_RLATENCY_1
#define ETHOSU_TA_RLATENCY_1 0
#endif
-#if ETHOSU_TA_WLATENCY_1 < 0
+
+#ifndef ETHOSU_TA_WLATENCY_1
#define ETHOSU_TA_WLATENCY_1 0
#endif
-#if ETHOSU_TA_PULSE_ON_1 < 0
+
+#ifndef ETHOSU_TA_PULSE_ON_1
#define ETHOSU_TA_PULSE_ON_1 0
#endif
-#if ETHOSU_TA_PULSE_OFF_1 < 0
+
+#ifndef ETHOSU_TA_PULSE_OFF_1
#define ETHOSU_TA_PULSE_OFF_1 0
#endif
-#if ETHOSU_TA_BWCAP_1 < 0
+
+#ifndef ETHOSU_TA_BWCAP_1
#define ETHOSU_TA_BWCAP_1 0
#endif
-#if ETHOSU_TA_PERFCTRL_1 < 0
+
+#ifndef ETHOSU_TA_PERFCTRL_1
#define ETHOSU_TA_PERFCTRL_1 0
#endif
-#if ETHOSU_TA_PERFCNT_1 < 0
+
+#ifndef ETHOSU_TA_PERFCNT_1
#define ETHOSU_TA_PERFCNT_1 0
#endif
-#if ETHOSU_TA_MODE_1 < 0
-#define ETHOSU_TA_MODE_1 0
+
+#ifndef ETHOSU_TA_MODE_1
+#define ETHOSU_TA_MODE_1 1
#endif
-#if ETHOSU_TA_HISTBIN_1 < 0
+
+#ifndef ETHOSU_TA_HISTBIN_1
#define ETHOSU_TA_HISTBIN_1 0
#endif
-#if ETHOSU_TA_HISTCNT_1 < 0
+
+#ifndef ETHOSU_TA_HISTCNT_1
#define ETHOSU_TA_HISTCNT_1 0
#endif