Rename .bss.NoInit section to .bss.tensor_arena
Change-Id: I660cd5d2bc73eaf589598c4f0570f5e9293de28d
diff --git a/applications/freertos/CMakeLists.txt b/applications/freertos/CMakeLists.txt
index 9581fe5..74cbe45 100644
--- a/applications/freertos/CMakeLists.txt
+++ b/applications/freertos/CMakeLists.txt
@@ -28,6 +28,6 @@
# Use the fast memory to support both 11.12.57 and 11.13.x release
# of the FVP
-# The size is defined to force the .bss.NoInit to be placed in DDR
+# The size is defined to force the .bss.tensor_arena to be placed in DDR
target_compile_definitions(
freertos PRIVATE ETHOSU_FAST_MEMORY_SIZE=0xa0000)
diff --git a/applications/freertos/main.cpp b/applications/freertos/main.cpp
index 4e58646..6f92faf 100644
--- a/applications/freertos/main.cpp
+++ b/applications/freertos/main.cpp
@@ -41,7 +41,7 @@
#define TENSOR_ARENA_SIZE 0xa0000
-__attribute__((section(".bss.NoInit"), aligned(16))) uint8_t inferenceProcessTensorArena[TENSOR_ARENA_SIZE];
+__attribute__((section(".bss.tensor_arena"), aligned(16))) uint8_t inferenceProcessTensorArena[TENSOR_ARENA_SIZE];
namespace {
diff --git a/applications/trustzone_inference/secure/main_secure.cpp b/applications/trustzone_inference/secure/main_secure.cpp
index 4c1b164..24d7dfb 100644
--- a/applications/trustzone_inference/secure/main_secure.cpp
+++ b/applications/trustzone_inference/secure/main_secure.cpp
@@ -44,7 +44,7 @@
****************************************************************************/
#define TENSOR_ARENA_SIZE 0xa0000
-__attribute__((section(".bss.NoInit"), aligned(16))) uint8_t TFLuTensorArena[TENSOR_ARENA_SIZE];
+__attribute__((section(".bss.tensor_arena"), aligned(16))) uint8_t TFLuTensorArena[TENSOR_ARENA_SIZE];
InferenceProcess::InferenceProcess inferenceProcess(TFLuTensorArena, TENSOR_ARENA_SIZE);
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
index 9365756..a1cdb0e 100644
--- a/targets/corstone-300/platform.ld
+++ b/targets/corstone-300/platform.ld
@@ -253,7 +253,7 @@
.sram :
{
. = ALIGN(16);
- *(.bss.NoInit)
+ *(.bss.tensor_arena)
. = ALIGN(16);
} > SRAM AT > SRAM
#else
@@ -264,10 +264,10 @@
. = ALIGN(16);
} > SRAM AT > SRAM
- .bss.NoInit :
+ .bss.tensor_arena :
{
. = ALIGN(16);
- *(.bss.NoInit)
+ *(.bss.tensor_arena)
. = ALIGN(16);
} > DDR AT > DDR
#endif
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter
index b8d5495..dc8f57b 100644
--- a/targets/corstone-300/platform.scatter
+++ b/targets/corstone-300/platform.scatter
@@ -1,7 +1,7 @@
#! cpp
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -113,7 +113,7 @@
{
#ifndef ETHOSU_FAST_MEMORY_SIZE
; Place tensor arena in SRAM if we do not have a fast memory area
- * (.bss.NoInit) ; Tensor Arena
+ * (.bss.tensor_arena)
#else
* (.bss.ethosu_scratch)
#endif
@@ -148,7 +148,7 @@
; Place tensor arena in DRAM if we have a fast memory area
ARENA +0 UNINIT ALIGN 16
{
- * (.bss.NoInit) ; Tensor Arena
+ * (.bss.tensor_arena)
}
#endif
#endif