Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /* |
| 20 | * Corstone-310 is the next generation Corstone-300 where the CPU |
| 21 | * has been upgraded to Cortex-M85. |
| 22 | * |
| 23 | * This is a simplified picture of the Corstone-310 memory system. |
| 24 | * Please refer to the Corstone SSE-310 Technical Reference Manual for |
| 25 | * further information. |
| 26 | * |
| 27 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 28 | * |
| 29 | * +---------------+ +---------------+ +------+ |
| 30 | * | Ethos-U55 | | Cortex-M85 +--+ ITCM | |
| 31 | * | | | | +------+ |
| 32 | * | | | | |
| 33 | * | | | | +------+ |
| 34 | * | M1 M0 | | +--+ DTCM | |
| 35 | * +---+-------+---+ +-------+-------+ +------+ |
| 36 | * | | | |
| 37 | * | +---+---------------+-----+ |
| 38 | * | | AMBA AXI NIC-400-Lite | |
| 39 | * | +---+-----------------+---+ |
| 40 | * | | | |
| 41 | * +---+-------+------------+ +--+-------+ |
| 42 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 43 | * +---+--------+--------+--+ | SRAM | |
| 44 | * | | | +----------+ |
| 45 | * +---+---+ +--+---+ +--+--+ |
| 46 | * | Flash | | BRAM | | DDR | |
| 47 | * +-------+ +------+ +-----+ |
| 48 | * |
| 49 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 50 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 51 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 52 | * | ITCM | 0x0000_0000 | 0x0000_8000 | NS | 32 kiB | |
| 53 | * | ITCM | 0x1000_0000 | 0x0000_8000 | S | Secure alias for NS ITCM | |
| 54 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 2 MiB | |
| 55 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | |
| 56 | * | DTCM | 0x2000_0000 | 0x0000_8000 | NS | 32 kiB | |
| 57 | * | DTCM | 0x3000_0000 | 0x0000_8000 | S | Secure alias for NS DTCM | |
| 58 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB; 3 cycles latency | |
| 59 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S | Secure alias for NS internal SRAM | |
| 60 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 256 MB bank | |
| 61 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | Secure alias for NS DDR | |
| 62 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 63 | * |
| 64 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 65 | * the model should only be placed in those regions. |
| 66 | * |
| 67 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 68 | * memory banks. |
| 69 | */ |
| 70 | |
| 71 | /* default value - '1', for DRAM */ |
| 72 | #ifndef ETHOSU_MODEL |
| 73 | #define ETHOSU_MODEL 1 |
| 74 | #endif |
| 75 | |
| 76 | /* default value - '1', for DRAM */ |
| 77 | #ifndef ETHOSU_ARENA |
| 78 | #define ETHOSU_ARENA 1 |
| 79 | #endif |
| 80 | |
| 81 | #ifndef STACK_SIZE |
| 82 | #define STACK_SIZE 0x8000 |
| 83 | #endif |
| 84 | |
| 85 | #ifndef HEAP_SIZE |
| 86 | #define HEAP_SIZE 0x10000 |
| 87 | #endif |
| 88 | |
| 89 | __STACK_SIZE = STACK_SIZE; |
| 90 | __HEAP_SIZE = HEAP_SIZE; |
| 91 | |
| 92 | MEMORY |
| 93 | { |
| 94 | ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 |
| 95 | BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00200000 |
| 96 | DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 |
| 97 | SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00400000 |
| 98 | QSPI (rw) : ORIGIN = 0x38000000, LENGTH = 0x00800000 |
| 99 | DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 |
| 100 | } |
| 101 | |
| 102 | PHDRS |
| 103 | { |
| 104 | rom_exec PT_LOAD; |
| 105 | rom_dram PT_LOAD; |
| 106 | null PT_NULL; |
| 107 | } |
| 108 | |
| 109 | /* Linker script to place sections and symbol values. Should be used together |
| 110 | * with other linker script that defines memory regions ITCM and RAM. |
| 111 | * It references following symbols, which must be defined in code: |
| 112 | * Reset_Handler : Entry of reset handler |
| 113 | * |
| 114 | * It defines following symbols, which code can use without definition: |
| 115 | * __exidx_start |
| 116 | * __exidx_end |
| 117 | * __copy_table_start__ |
| 118 | * __copy_table_end__ |
| 119 | * __zero_table_start__ |
| 120 | * __zero_table_end__ |
| 121 | * __etext |
| 122 | * __data_start__ |
| 123 | * __preinit_array_start |
| 124 | * __preinit_array_end |
| 125 | * __init_array_start |
| 126 | * __init_array_end |
| 127 | * __fini_array_start |
| 128 | * __fini_array_end |
| 129 | * __data_end__ |
| 130 | * __bss_start__ |
| 131 | * __bss_end__ |
| 132 | * __end__ |
| 133 | * end |
| 134 | * __HeapLimit |
| 135 | * __StackLimit |
| 136 | * __StackTop |
| 137 | * __stack |
| 138 | */ |
| 139 | |
| 140 | ENTRY(Reset_Handler) |
| 141 | |
| 142 | SECTIONS |
| 143 | { |
| 144 | .text : |
| 145 | { |
| 146 | KEEP(*(.vectors)) |
| 147 | *crt* (.text*) |
Davide Grohmann | a8832cc | 2022-05-06 16:35:16 +0200 | [diff] [blame] | 148 | *startup_ARMCM85.c.obj (.text*) |
| 149 | *system_ARMCM85.c.obj (.text*) |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 150 | *target.cpp.obj (.text*) |
| 151 | |
| 152 | KEEP(*(.init)) |
| 153 | KEEP(*(.fini)) |
| 154 | |
| 155 | /* .ctors */ |
| 156 | *crtbegin.o(.ctors) |
| 157 | *crtbegin?.o(.ctors) |
| 158 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 159 | *(SORT(.ctors.*)) |
| 160 | *(.ctors) |
| 161 | |
| 162 | /* .dtors */ |
| 163 | *crtbegin.o(.dtors) |
| 164 | *crtbegin?.o(.dtors) |
| 165 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 166 | *(SORT(.dtors.*)) |
| 167 | *(.dtors) |
| 168 | |
| 169 | *(.text*) |
| 170 | |
| 171 | KEEP(*(.eh_frame*)) |
| 172 | } > BRAM :rom_exec |
| 173 | |
| 174 | .data : |
| 175 | { |
| 176 | . = ALIGN(4); |
| 177 | __data_start__ = .; |
| 178 | |
| 179 | *(vtable) |
| 180 | *(.data) |
| 181 | *(.data.*) |
| 182 | *(.rodata*) |
| 183 | |
| 184 | . = ALIGN(4); |
| 185 | __data_end__ = .; |
| 186 | } > BRAM :rom_exec |
| 187 | |
| 188 | /* |
| 189 | * SG veneers: |
| 190 | * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address |
| 191 | * must be set, either with the command line option '--section-start' or in a linker script, |
| 192 | * to indicate where to place these veneers in memory. |
| 193 | */ |
| 194 | /* |
| 195 | .gnu.sgstubs : |
| 196 | { |
| 197 | . = ALIGN(32); |
| 198 | } > BRAM :rom_exec |
| 199 | */ |
| 200 | .ARM.extab : |
| 201 | { |
| 202 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
| 203 | } > BRAM :rom_exec |
| 204 | |
| 205 | .ARM.exidx : |
| 206 | { |
| 207 | __exidx_start = .; |
| 208 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| 209 | __exidx_end = .; |
| 210 | } > BRAM :rom_exec |
| 211 | |
| 212 | .copy.table : |
| 213 | { |
| 214 | . = ALIGN(4); |
| 215 | __copy_table_start__ = .; |
| 216 | |
| 217 | LONG (LOADADDR(.sram)) |
| 218 | LONG (ADDR(.sram)) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 219 | LONG (SIZEOF(.sram) / 4) |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 220 | |
| 221 | __copy_table_end__ = .; |
| 222 | } > BRAM :rom_exec |
| 223 | |
| 224 | .zero.table : |
| 225 | { |
| 226 | . = ALIGN(4); |
| 227 | __zero_table_start__ = .; |
| 228 | |
| 229 | LONG (ADDR(.bss)) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 230 | LONG (SIZEOF(.bss) / 4) |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 231 | |
| 232 | LONG (ADDR(.sram.bss)) |
Davide Grohmann | 8b53aad | 2022-05-05 17:15:19 +0200 | [diff] [blame] | 233 | LONG (SIZEOF(.sram.bss) / 4) |
Kristofer Jonsson | 9317581 | 2022-04-21 19:27:11 +0200 | [diff] [blame] | 234 | |
| 235 | __zero_table_end__ = .; |
| 236 | } > BRAM :rom_exec |
| 237 | |
| 238 | .sram : AT(__etext) |
| 239 | { |
| 240 | #if (ETHOSU_MODEL == 0) |
| 241 | . = ALIGN(16); |
| 242 | *(network_model_sec) |
| 243 | #endif |
| 244 | |
| 245 | . = ALIGN(16); |
| 246 | *(.sram.data) |
| 247 | |
| 248 | . = ALIGN(4); |
| 249 | /* preinit data */ |
| 250 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 251 | KEEP(*(.preinit_array)) |
| 252 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 253 | |
| 254 | . = ALIGN(4); |
| 255 | /* init data */ |
| 256 | PROVIDE_HIDDEN (__init_array_start = .); |
| 257 | KEEP(*(SORT(.init_array.*))) |
| 258 | KEEP(*(.init_array)) |
| 259 | PROVIDE_HIDDEN (__init_array_end = .); |
| 260 | |
| 261 | . = ALIGN(4); |
| 262 | /* finit data */ |
| 263 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 264 | KEEP(*(SORT(.fini_array.*))) |
| 265 | KEEP(*(.fini_array)) |
| 266 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 267 | |
| 268 | KEEP(*(.jcr*)) |
| 269 | } > SRAM :rom_dram |
| 270 | |
| 271 | .sram.bss : |
| 272 | { |
| 273 | #if (ETHOSU_ARENA == 0) |
| 274 | . = ALIGN(16); |
| 275 | *(.bss.tensor_arena) |
| 276 | #endif |
| 277 | |
| 278 | . = ALIGN(16); |
| 279 | *(.bss.ethosu_scratch); |
| 280 | } > SRAM :null |
| 281 | |
| 282 | .ddr : |
| 283 | { |
| 284 | #if (ETHOSU_ARENA == 1) |
| 285 | . = ALIGN(16); |
| 286 | *(.bss.tensor_arena) |
| 287 | #endif |
| 288 | |
| 289 | #if (ETHOSU_MODEL == 1) |
| 290 | . = ALIGN(16); |
| 291 | *(network_model_sec) |
| 292 | #endif |
| 293 | |
| 294 | . = ALIGN(4); |
| 295 | *(input_data_sec) |
| 296 | *(expected_output_data_sec) |
| 297 | *(output_data_sec) |
| 298 | |
| 299 | *(ethosu_core_in_queue ethosu_core_out_queue) |
| 300 | |
| 301 | /* Place data for scatter loading here */ |
| 302 | __etext = .; |
| 303 | } > DDR :rom_dram |
| 304 | |
| 305 | .bss : |
| 306 | { |
| 307 | . = ALIGN(4); |
| 308 | __bss_start__ = .; |
| 309 | |
| 310 | *(.bss) |
| 311 | *(.bss.*) |
| 312 | *(COMMON) |
| 313 | |
| 314 | . = ALIGN(4); |
| 315 | __bss_end__ = .; |
| 316 | } > BRAM :null |
| 317 | |
| 318 | .heap (COPY) : |
| 319 | { |
| 320 | . = ALIGN(8); |
| 321 | __end__ = .; |
| 322 | PROVIDE(end = .); |
| 323 | . = . + __HEAP_SIZE; |
| 324 | . = ALIGN(8); |
| 325 | __HeapLimit = .; |
| 326 | } > BRAM :null |
| 327 | |
| 328 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 329 | { |
| 330 | . = ALIGN(8); |
| 331 | __StackLimit = .; |
| 332 | . = . + __STACK_SIZE; |
| 333 | . = ALIGN(8); |
| 334 | __StackTop = .; |
| 335 | } > DTCM :null |
| 336 | PROVIDE(__stack = __StackTop); |
| 337 | |
| 338 | /* Check if data + heap + stack exceeds DTCM limit */ |
| 339 | ASSERT(LENGTH(DTCM) >= __STACK_SIZE, "region DTCM overflowed with stack") |
| 340 | } |