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review.mlplatform.org / ml / ethos-u / ethos-u-core-platform / 5508acb0c7803769b9bbda08762b232c13272bd9 / . / targets / corstone-310 / target.cpp
blob: 3b2820f81457158d52e76d7b4431ee6717ae4ddb [file] [log] [blame]
Kristofer Jonsson93175812022-04-21 19:27:11 +0200[diff] [blame]1/*
2 * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/****************************************************************************
20 * Includes
21 ****************************************************************************/
22
23#include "target.hpp"
24
25#ifdef ETHOSU
26#include <ethosu_driver.h>
27#include <timing_adapter.h>
28#endif
29
30#include "mpu.hpp"
31#include "uart_stdout.h"
32
33#include <inttypes.h>
34#include <stdio.h>
35#include <stdlib.h>
36#include <vector>
37
38using namespace EthosU;
39
40/****************************************************************************
41 * Defines
42 ****************************************************************************/
43
44#define ETHOSU_BASE_ADDRESS 0x50004000
45#define ETHOSU_IRQ 16
46
47#define ETHOSU0_TA0_BASE_ADDRESS 0x58103000
48#define ETHOSU0_TA1_BASE_ADDRESS 0x58103200
49
50/****************************************************************************
51 * Variables
52 ****************************************************************************/
53
54#if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0
55__attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE];
56#else
57#define ethosu_scratch 0
58#define ETHOSU_FAST_MEMORY_SIZE 0
59#endif
60
61#ifdef ETHOSU
62struct ethosu_driver ethosu0_driver;
63#endif
64
65/****************************************************************************
66 * Timing Adapters
67 ****************************************************************************/
68
69#ifdef ETHOSU
70
71#ifndef ETHOSU_TA_MAXR_0
72#define ETHOSU_TA_MAXR_0 0
73#endif
74
75#ifndef ETHOSU_TA_MAXW_0
76#define ETHOSU_TA_MAXW_0 0
77#endif
78
79#ifndef ETHOSU_TA_MAXRW_0
80#define ETHOSU_TA_MAXRW_0 0
81#endif
82
83#ifndef ETHOSU_TA_RLATENCY_0
84#define ETHOSU_TA_RLATENCY_0 0
85#endif
86
87#ifndef ETHOSU_TA_WLATENCY_0
88#define ETHOSU_TA_WLATENCY_0 0
89#endif
90
91#ifndef ETHOSU_TA_PULSE_ON_0
92#define ETHOSU_TA_PULSE_ON_0 0
93#endif
94
95#ifndef ETHOSU_TA_PULSE_OFF_0
96#define ETHOSU_TA_PULSE_OFF_0 0
97#endif
98
99#ifndef ETHOSU_TA_BWCAP_0
100#define ETHOSU_TA_BWCAP_0 0
101#endif
102
103#ifndef ETHOSU_TA_PERFCTRL_0
104#define ETHOSU_TA_PERFCTRL_0 0
105#endif
106
107#ifndef ETHOSU_TA_PERFCNT_0
108#define ETHOSU_TA_PERFCNT_0 0
109#endif
110
111#ifndef ETHOSU_TA_MODE_0
112#define ETHOSU_TA_MODE_0 1
113#endif
114
115#ifndef ETHOSU_TA_HISTBIN_0
116#define ETHOSU_TA_HISTBIN_0 0
117#endif
118
119#ifndef ETHOSU_TA_HISTCNT_0
120#define ETHOSU_TA_HISTCNT_0 0
121#endif
122
123#ifndef ETHOSU_TA_MAXR_1
124#define ETHOSU_TA_MAXR_1 0
125#endif
126
127#ifndef ETHOSU_TA_MAXW_1
128#define ETHOSU_TA_MAXW_1 0
129#endif
130
131#ifndef ETHOSU_TA_MAXRW_1
132#define ETHOSU_TA_MAXRW_1 0
133#endif
134
135#ifndef ETHOSU_TA_RLATENCY_1
136#define ETHOSU_TA_RLATENCY_1 0
137#endif
138
139#ifndef ETHOSU_TA_WLATENCY_1
140#define ETHOSU_TA_WLATENCY_1 0
141#endif
142
143#ifndef ETHOSU_TA_PULSE_ON_1
144#define ETHOSU_TA_PULSE_ON_1 0
145#endif
146
147#ifndef ETHOSU_TA_PULSE_OFF_1
148#define ETHOSU_TA_PULSE_OFF_1 0
149#endif
150
151#ifndef ETHOSU_TA_BWCAP_1
152#define ETHOSU_TA_BWCAP_1 0
153#endif
154
155#ifndef ETHOSU_TA_PERFCTRL_1
156#define ETHOSU_TA_PERFCTRL_1 0
157#endif
158
159#ifndef ETHOSU_TA_PERFCNT_1
160#define ETHOSU_TA_PERFCNT_1 0
161#endif
162
163#ifndef ETHOSU_TA_MODE_1
164#define ETHOSU_TA_MODE_1 1
165#endif
166
167#ifndef ETHOSU_TA_HISTBIN_1
168#define ETHOSU_TA_HISTBIN_1 0
169#endif
170
171#ifndef ETHOSU_TA_HISTCNT_1
172#define ETHOSU_TA_HISTCNT_1 0
173#endif
174
Henrik Hoglindebe33a42022-06-17 11:32:17 +0200[diff] [blame]175#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2
Kristofer Jonsson93175812022-04-21 19:27:11 +0200[diff] [blame]176static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = {
177 {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}};
178struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT];
179struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0,
180 ETHOSU_TA_MAXW_0,
181 ETHOSU_TA_MAXRW_0,
182 ETHOSU_TA_RLATENCY_0,
183 ETHOSU_TA_WLATENCY_0,
184 ETHOSU_TA_PULSE_ON_0,
185 ETHOSU_TA_PULSE_OFF_0,
186 ETHOSU_TA_BWCAP_0,
187 ETHOSU_TA_PERFCTRL_0,
188 ETHOSU_TA_PERFCNT_0,
189 ETHOSU_TA_MODE_0,
190 0, // Read only register
191 ETHOSU_TA_HISTBIN_0,
192 ETHOSU_TA_HISTCNT_0},
193 {ETHOSU_TA_MAXR_1,
194 ETHOSU_TA_MAXW_1,
195 ETHOSU_TA_MAXRW_1,
196 ETHOSU_TA_RLATENCY_1,
197 ETHOSU_TA_WLATENCY_1,
198 ETHOSU_TA_PULSE_ON_1,
199 ETHOSU_TA_PULSE_OFF_1,
200 ETHOSU_TA_BWCAP_1,
201 ETHOSU_TA_PERFCTRL_1,
202 ETHOSU_TA_PERFCNT_1,
203 ETHOSU_TA_MODE_1,
204 0, // Read only register
205 ETHOSU_TA_HISTBIN_1,
206 ETHOSU_TA_HISTCNT_1}};
Henrik Hoglindebe33a42022-06-17 11:32:17 +0200[diff] [blame]207#endif
Kristofer Jonsson93175812022-04-21 19:27:11 +0200[diff] [blame]208
209#endif
210
211/****************************************************************************
212 * Cache maintenance
213 ****************************************************************************/
214
215#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
216extern "C" {
217void ethosu_flush_dcache(uint32_t *p, size_t bytes) {
218 if (p)
219 SCB_CleanDCache_by_Addr(p, bytes);
220 else
221 SCB_CleanDCache();
222}
223
224void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) {
225 if (p)
226 SCB_InvalidateDCache_by_Addr(p, bytes);
227 else
228 SCB_InvalidateDCache();
229}
230}
231#endif
232
233/****************************************************************************
234 * Init
235 ****************************************************************************/
236
237namespace {
238
239extern "C" {
240struct ExcContext {
241 uint32_t r0;
242 uint32_t r1;
243 uint32_t r2;
244 uint32_t r3;
245 uint32_t r12;
246 uint32_t lr;
247 uint32_t pc;
248 uint32_t xPsr;
249};
250
251void HardFault_Handler() {
252 int irq;
253 struct ExcContext *e;
254 uint32_t sp;
255
256 asm volatile("mrs %0, ipsr \n" // Read IPSR (Exceptio number)
257 "sub %0, #16 \n" // Get it into IRQn_Type range
258 "tst lr, #4 \n" // Select the stack which was in use
259 "ite eq \n"
260 "mrseq %1, msp \n"
261 "mrsne %1, psp \n"
262 "mov %2, sp \n"
263 : "=r"(irq), "=r"(e), "=r"(sp));
264
265 printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n",
266 irq,
267 e->pc,
268 e->lr,
269 e->xPsr,
270 sp);
271 printf(
272 "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR);
273 exit(1);
274}
275}
276
277#ifdef ETHOSU
278void ethosuIrqHandler() {
279 ethosu_irq_handler(&ethosu0_driver);
280}
281#endif
282
283} // namespace
284
285namespace EthosU {
286
287void targetSetup() {
288 // Initialize UART driver
289 UartStdOutInit();
290
291#ifdef ETHOSU
292 // Initialize timing adapter(s)
293 for (int i = 0; i < ETHOSU_NPU_COUNT; i++) {
Henrik Hoglindebe33a42022-06-17 11:32:17 +0200[diff] [blame]294#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2
Kristofer Jonsson93175812022-04-21 19:27:11 +0200[diff] [blame]295 for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) {
296 if (ta_init(&ethosu_ta[i][j], ethosu_ta_base_addrs[i][j])) {
297 printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i);
298 } else {
299 // Set the updated configuration
300 ta_set_all(&ethosu_ta[i][j], &ethosu_ta_settings[j]);
301 }
302 }
Henrik Hoglindebe33a42022-06-17 11:32:17 +0200[diff] [blame]303#endif
Kristofer Jonsson93175812022-04-21 19:27:11 +0200[diff] [blame]304 }
305
306 // Initialize Ethos-U NPU driver
307 if (ethosu_init(&ethosu0_driver,
308 reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS),
309 ethosu_scratch,
310 ETHOSU_FAST_MEMORY_SIZE,
311 1,
312 1)) {
313 printf("Failed to initialize NPU.\n");
314 return;
315 }
316
317 // Assumes SCB->VTOR point to RW memory
318 NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)&ethosuIrqHandler);
319 NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ));
320#endif
321
322 // MPU setup
323 const std::vector<ARM_MPU_Region_t> mpuConfig = {
324 {
325 // ITCM (NS)
326 ARM_MPU_RBAR(0x00000000, // Base
327 ARM_MPU_SH_NON, // Non-shareable
328 1, // Read-Only
329 1, // Non-Privileged
330 0), // eXecute Never disabled
331 ARM_MPU_RLAR(0x00007fff, // Limit
332 Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
333 },
334 {
335 // ITCM (S)
336 ARM_MPU_RBAR(0x10000000, // Base
337 ARM_MPU_SH_NON, // Non-shareable
338 1, // Read-Only
339 1, // Non-Privileged
340 0), // eXecute Never disabled
341 ARM_MPU_RLAR(0x10007fff, // Limit
342 Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate
343 },
344 {
345 // DTCM (NS)
346 ARM_MPU_RBAR(0x20000000, // Base
347 ARM_MPU_SH_NON, // Non-shareable
348 0, // Read-Write
349 1, // Non-Privileged
350 1), // eXecute Never enabled
351 ARM_MPU_RLAR(0x20007fff, // Limit
352 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
353 },
354 {
355 // DTCM (S)
356 ARM_MPU_RBAR(0x30000000, // Base
357 ARM_MPU_SH_NON, // Non-shareable
358 0, // Read-Write
359 1, // Non-Privileged
360 1), // eXecute Never enabled
361 ARM_MPU_RLAR(0x30007fff, // Limit
362 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
363 },
364 {
365 // FPGA DATA SRAM; BRAM (NS)
366 ARM_MPU_RBAR(0x01000000, // Base
367 ARM_MPU_SH_NON, // Non-shareable
368 0, // Read-Write
369 1, // Non-Privileged
370 0), // eXecute Never disabled
371 ARM_MPU_RLAR(0x011fffff, // Limit
372 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
373 },
374 {
375 // FPGA DATA SRAM; BRAM (S)
376 ARM_MPU_RBAR(0x11000000, // Base
377 ARM_MPU_SH_NON, // Non-shareable
378 0, // Read-Write
379 1, // Non-Privileged
380 0), // eXecute Never disabled
381 ARM_MPU_RLAR(0x111fffff, // Limit
382 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
383 },
384 {
385 // SSE-300 internal SRAM (NS)
386 ARM_MPU_RBAR(0x21000000, // Base
387 ARM_MPU_SH_NON, // Non-shareable
388 0, // Read-Write
389 1, // Non-Privileged
390 0), // eXecute Never disabled
391 ARM_MPU_RLAR(0x213fffff, // Limit
392 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
393 },
394 {
395 // SSE-300 internal SRAM (S)
396 ARM_MPU_RBAR(0x31000000, // Base
397 ARM_MPU_SH_NON, // Non-shareable
398 0, // Read-Write
399 1, // Non-Privileged
400 0), // eXecute Never disabled
401 ARM_MPU_RLAR(0x313fffff, // Limit
402 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
403 },
404 {
405 // DDR (NS)
406 ARM_MPU_RBAR(0x60000000, // Base
407 ARM_MPU_SH_NON, // Non-shareable
408 0, // Read-Write
409 1, // Non-Privileged
410 1), // eXecute Never enabled
411 ARM_MPU_RLAR(0x6fffffff, // Limit
412 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
413 },
414 {
415 // DDR (S)
416 ARM_MPU_RBAR(0x70000000, // Base
417 ARM_MPU_SH_NON, // Non-shareable
418 0, // Read-Write
419 1, // Non-Privileged
420 1), // eXecute Never enabled
421 ARM_MPU_RLAR(0x7fffffff, // Limit
422 Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate
423 }};
424
425 // Setup MPU configuration
426 Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size());
427
428#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
429 SCB_EnableICache();
430 SCB_EnableDCache();
431#endif
432}
433
434} // namespace EthosU