Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | #ifndef TIMING_ADAPTER_H_ |
| 20 | #define TIMING_ADAPTER_H_ |
| 21 | |
| 22 | #include <stdint.h> |
| 23 | |
| 24 | #if defined __cplusplus |
| 25 | extern "C" { |
| 26 | #endif |
| 27 | |
| 28 | /** TIMING ADAPTER |
| 29 | * |
| 30 | * The timing adapter is an AXI-to-AXI bridge for providing well-defined memory timing |
Ledion Daja | 09d4945 | 2022-02-02 15:26:53 +0100 | [diff] [blame] | 31 | * to allow performance evaluation of an AXI manager. The bridge works by delaying the |
Yulia Garbovich | e9cdc63 | 2021-11-23 20:00:04 +0200 | [diff] [blame] | 32 | * responses from the memory according to run-time configurable parameters that can be |
| 33 | * set in the timing adapter. Parameters include read and write response latencies, |
| 34 | * no. of outstanding transactions, and a model of interferring traffic. |
| 35 | */ |
| 36 | |
| 37 | struct timing_adapter { |
| 38 | uintptr_t base_addr; |
| 39 | }; |
| 40 | |
| 41 | /** LIMITATIONS FOR FVP: |
| 42 | * |
| 43 | * - TA_MODE is hardcoded to 1 (one) at all times. |
| 44 | * - Only TA_PERFCTRL_AWTRANS and TA_PERFCTRL_ARTRANS support is |
| 45 | * implemented for the performance counter. |
| 46 | */ |
| 47 | |
| 48 | struct timing_adapter_settings { |
| 49 | uint32_t maxr; // 6-bit field. Max no. of pending reads. 0=infinite |
| 50 | uint32_t maxw; // 6-bit field. Max no. of pending writes. 0=infinite |
| 51 | uint32_t maxrw; // 6-bit field. Max no. of pending reads+writes. 0=infinite |
| 52 | uint32_t rlatency; // 12-bit field. Minimum latency (clock cycles) from AVALID to RVALID. |
| 53 | uint32_t wlatency; // 12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID. |
| 54 | uint32_t pulse_on; // No. of cycles addresses let through (0-65535). |
| 55 | uint32_t pulse_off; // No. of cycles addresses blocked (0-65535). |
| 56 | uint32_t bwcap; // 16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite |
| 57 | uint32_t perfctrl; // 6-bit field selecting an event for event counter 0=default |
| 58 | uint32_t perfcnt; // 32-bit event counter |
| 59 | uint32_t mode; // Bit 0: 1=enable dynamic clocking to avoid underrun |
| 60 | // Bit 1: 1=enable random AR reordering (0=default) |
| 61 | // Bit 2: 1=enable random R reordering (0=default) |
| 62 | // Bit 3: 1=enable random B reordering (0=default) |
| 63 | // Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed |
| 64 | uint32_t maxpending; // (Read-only) Max supported value in MAXR and MAXW registers |
| 65 | uint32_t histbin; // Controlls which histogram bin (0-15) that should be accessed by HISTCNT. |
| 66 | uint32_t histcnt; // 32-bit field. Read/write the selected histogram bin. |
| 67 | }; |
| 68 | |
| 69 | enum timing_adapter_perfctrl_settings { |
| 70 | TA_PERFCTRL_OFF = 0, // Disable performance counting |
| 71 | TA_PERFCTRL_CYCLES, // Count all cycles (root clock) |
| 72 | TA_PERFCTRL_UNDERRUN_R, // Unable to meet RLATENCY deadline |
| 73 | TA_PERFCTRL_UNDERRUN_B, // Unable to meet WLATENCY deadline |
| 74 | TA_PERFCTRL_OVERFLOW_AR, // Internal read address FIFO full |
| 75 | TA_PERFCTRL_OVERFLOW_AW, // Internal write address FIFO full |
| 76 | TA_PERFCTRL_OVERFLOW_R, // Internal read data FIFO full |
| 77 | TA_PERFCTRL_OVERFLOW_W, // Internal write data FIFO full |
| 78 | TA_PERFCTRL_OVERFLOW_B, // Internal write response FIFO full |
| 79 | TA_PERFCTRL_RREADY, // RREADY wait state |
| 80 | TA_PERFCTRL_BREADY, // BREADY wait state |
| 81 | TA_PERFCTRL_RTRANS, // Handshake on R channel |
| 82 | TA_PERFCTRL_WTRANS, // Handshake on W channel |
| 83 | TA_PERFCTRL_BTRANS, // Handshake on B channel |
| 84 | TA_PERFCTRL_ARTRANS, // Handshake on AR channel |
| 85 | TA_PERFCTRL_AWTRANS, // Handshake on AW channel |
| 86 | TA_PERFCTRL_ARQTIME, // Histogram of how much time spent with outstanding read transactions |
| 87 | TA_PERFCTRL_AWQTIME, // Histogram of how much time spent with outstanding write transactions |
| 88 | TA_PERFCTRL_MCLK_ON, // Count cycles when DUT clock is on |
| 89 | TA_PERFCTRL_MCLK_OFF, // Count cycles when DUT clock is off |
| 90 | TA_PERFCTRL_ARLEN0 = 32, // Handshake on AR channel with ARLEN=0 |
| 91 | TA_PERFCTRL_AWLEN0 = 48 // Handshake on AW channel with AWLEN=0 |
| 92 | }; |
| 93 | |
| 94 | int ta_init(struct timing_adapter *ta, uintptr_t base_addr); |
| 95 | void ta_uninit(struct timing_adapter *ta); |
| 96 | |
| 97 | void ta_set_all(struct timing_adapter *ta, struct timing_adapter_settings *in); |
| 98 | void ta_set_maxr(struct timing_adapter *ta, uint32_t val); |
| 99 | void ta_set_maxw(struct timing_adapter *ta, uint32_t val); |
| 100 | void ta_set_maxrw(struct timing_adapter *ta, uint32_t val); |
| 101 | void ta_set_rlatency(struct timing_adapter *ta, uint32_t val); |
| 102 | void ta_set_wlatency(struct timing_adapter *ta, uint32_t val); |
| 103 | void ta_set_pulse_on(struct timing_adapter *ta, uint32_t val); |
| 104 | void ta_set_pulse_off(struct timing_adapter *ta, uint32_t val); |
| 105 | void ta_set_bwcap(struct timing_adapter *ta, uint32_t val); |
| 106 | void ta_set_perfctrl(struct timing_adapter *ta, uint32_t val); |
| 107 | void ta_set_perfcnt(struct timing_adapter *ta, uint32_t val); |
| 108 | void ta_set_mode(struct timing_adapter *ta, uint32_t val); |
| 109 | void ta_set_histbin(struct timing_adapter *ta, uint32_t val); |
| 110 | void ta_set_histcnt(struct timing_adapter *ta, uint32_t val); |
| 111 | |
| 112 | void ta_get_all(struct timing_adapter *ta, struct timing_adapter_settings *out); |
| 113 | uint32_t ta_get_maxr(struct timing_adapter *ta); |
| 114 | uint32_t ta_get_maxw(struct timing_adapter *ta); |
| 115 | uint32_t ta_get_maxrw(struct timing_adapter *ta); |
| 116 | uint32_t ta_get_rlatency(struct timing_adapter *ta); |
| 117 | uint32_t ta_get_wlatency(struct timing_adapter *ta); |
| 118 | uint32_t ta_get_pulse_on(struct timing_adapter *ta); |
| 119 | uint32_t ta_get_pulse_off(struct timing_adapter *ta); |
| 120 | uint32_t ta_get_bwcap(struct timing_adapter *ta); |
| 121 | uint32_t ta_get_perfctrl(struct timing_adapter *ta); |
| 122 | uint32_t ta_get_perfcnt(struct timing_adapter *ta); |
| 123 | uint32_t ta_get_mode(struct timing_adapter *ta); |
| 124 | uint32_t ta_get_maxpending(struct timing_adapter *ta); |
| 125 | uint32_t ta_get_histbin(struct timing_adapter *ta); |
| 126 | uint32_t ta_get_histcnt(struct timing_adapter *ta); |
| 127 | uint32_t ta_get_version(struct timing_adapter *ta); |
| 128 | |
| 129 | #if defined __cplusplus |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | #endif |