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review.mlplatform.org / ml / ethos-u / ethos-u-core-software / ae4d83089982e9d9fb11e7152bf9442b220d8b01 / . / drivers / mhu_v2 / include / mhu_v2.hpp
blob: 881c0ea7770e9d3e3619a4e008c6b3ef115fcbc2 [file] [log] [blame]
Jonny Svärd9fc527b2020-11-16 16:18:07 +0100[diff] [blame]1/*
2 * Copyright (c) 2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#ifndef MHU_V2_HPP
20#define MHU_V2_HPP
21
22#include <mailbox.hpp>
23
24#include <cstddef>
25#include <cstdint>
26#include <cstdio>
27#include <cstring>
28
29namespace Mailbox {
30/*
31 * SENDER OVERVIEW
32 * ------------------------------------------------------------------------
33 * Offset Access Type Register Name Short Name
34 * ------------------------------------------------------------------------
35 * 0x000-0xF7C - Sender Channel Window 0-123 -
36 * 0xF80 RO Message Handling Unit Configuration MHU_CFG
37 * 0xF84 RW Response Configuration RESP_CFG
38 * 0xF88 RW Access Request ACCESS_REQUEST
39 * 0xF8C RO Access Ready ACCESS_READY
40 * 0xF90 RO Interrupt Status INT_ST
41 * 0xF94 WO Interrupt Clear INT_CLR
42 * 0xF98 RW Interrupt Enable INT_EN
43 * 0xF9C-0xFC4 RO Reserved -
44 * 0xFC8 RO Implementer Identification Register IIDR
45 * 0xFCC RO Architecture Identification Register AIDR
46 * 0xFD0-0xFFC - IMPL DEF Identification Regs -
47 */
48
49/*
50 * RECEIVER OVERVIEW
51 * ------------------------------------------------------------------------
52 * Offset Access Type Register Name Short Name
53 * ------------------------------------------------------------------------
54 * 0x000-0xF7C - Receiver Channel Window 0-123 -
55 * 0xF80 RO Message Handling Unit Configuration MHU_CFG
56 * 0xF84-0xFC4 RO Reserved -
57 * 0xFC8 RO Implementer Identification Register IIDR
58 * 0xFCC RO Architecture Identification Register AIDR
59 * 0xFD0-0xFFC - IMPL DEF Identification Regs -
60 */
61
62/*
63 * Sender Channel Window
64 * ------------------------------------------------------------------------
65 * Offset Access Type Register Name Short Name
66 * ------------------------------------------------------------------------
67 * 0x00 RO Channel Status CH_ST
68 * 0x04 RO Reserved -
69 * 0x08 RO Reserved -
70 * 0x0C WO Channel Set CH_SET
71 * 0x10 RO Reserved -
72 * 0x14 RO Reserved -
73 * 0x18 RO Reserved -
74 * 0x1C RO Reserved -
75 */
76
77/*
78 * Receiver Channel Window
79 * ------------------------------------------------------------------------
80 * Offset Access Type Register Name Short Name
81 * ------------------------------------------------------------------------
82 * 0x00 RO Channel Status CH_ST
83 * 0x04 RO Channel Status Masked CH_ST_MSK
84 * 0x08 WO Channel Clear CH_CLR
85 * 0x0C RO Reserved -
86 * 0x10 RO Channel Mask Status CH_MSK_ST
87 * 0x14 WO Channel Mask Set CH_MSK_SET
88 * 0x18 WO Channel Mask Clear CH_MSK_CLR
89 * 0x1C RO Reserved -
90 */
91
92// Doorbell implementation only
93// NOTE: MHUv2 is unidirectional. Two MHU's are needed for bidirectional
94// messaging. txBase/rxBase refers to the base address of _two_
95// separate MHU blocks.
96class MHUv2 : public Mailbox {
97public:
98 MHUv2(const uint32_t txBaseAddress, const uint32_t rxBaseAddress);
99 virtual ~MHUv2();
100 virtual bool sendMessage() final;
101 virtual void handleMessage() final;
102 virtual bool verifyHardware() final;
103
104private:
105 /* Offsets */
106 static constexpr uint32_t MHUv2_CH_ST = 0x00;
107 static constexpr uint32_t MHUv2_CH_ST_MSK = 0x04;
108 static constexpr uint32_t MHUv2_CH_CLR = 0x08;
109 static constexpr uint32_t MHUv2_CH_SET = 0x0C;
110 static constexpr uint32_t MHUv2_CH_MSK_ST = 0x10;
111 static constexpr uint32_t MHUv2_CH_MSK_SET = 0x14;
112 static constexpr uint32_t MHUv2_CH_MSK_CLR = 0x18;
113 static constexpr uint32_t MHUv2_CH_INT_CLR = 0x14;
114 static constexpr uint32_t MHUv2_CH_INT_EN = 0x18;
115 static constexpr uint32_t MHUv2_SND_CHAN_WINDOW_SIZE = 0x20;
116 static constexpr uint32_t MHUv2_SND_MHU_CFG_OFFS = 0xF80;
117 static constexpr uint32_t MHUv2_SND_RESP_CFG_OFFS = 0xF84;
118 static constexpr uint32_t MHUv2_SND_ACCESS_REQUEST_OFFS = 0xF88;
119 static constexpr uint32_t MHUv2_SND_ACCESS_READY_OFFS = 0xF8C;
120 static constexpr uint32_t MHUv2_SND_INT_ST_OFFS = 0xF90;
121 static constexpr uint32_t MHUv2_SND_INT_CLR_OFFS = 0xF94;
122 static constexpr uint32_t MHUv2_SND_INT_EN_OFFS = 0xF98;
123 static constexpr uint32_t MHUv2_SND_IIDR_OFFS = 0xFC8;
124 static constexpr uint32_t MHUv2_SND_AIDR_OFFS = 0xFCC;
125 static constexpr uint32_t MHUv2_RCV_CHAN_WINDOW_SIZE = 0x20;
126 static constexpr uint32_t MHUv2_RCV_MHU_CFG_OFFS = 0xF80;
127 static constexpr uint32_t MHUv2_RCV_IIDR_OFFS = 0xFC8;
128 static constexpr uint32_t MHUv2_RCV_AIDR_OFFS = 0xFCC;
129 static constexpr uint32_t MHUv2_RCV_INT_EN_OFFS = 0xF98;
130
131 struct aidr_t {
132 uint32_t ARCH_MINOR_REV : 4;
133 uint32_t ARCH_MAJOR_REV : 4;
134 uint32_t RESERVED : 24;
135 };
136
137 volatile uint32_t *txBaseAddr;
138 volatile uint32_t *rxBaseAddr;
139
140 void clearMessage();
141 void printAIDR(bool tx = true, bool rx = true);
142
143 void txWrite(uint32_t offset, uint32_t value);
144 void rxWrite(uint32_t offset, uint32_t value);
145 uint32_t txRead(uint32_t offset);
146 uint32_t rxRead(uint32_t offset);
147
148 // Sender/tx
149 uint32_t getAccessReady();
150 uint32_t getAccessRequest();
151 uint32_t getInterruptStatus();
152 uint32_t getTxAIDR();
153 uint32_t getTxStatusForChan(uint8_t chan);
154 void enableAccessRequest();
155 void disableAccessRequest();
156 void setCombinedClearInterrupt(bool enable);
157 void setReadyNotReadyInterrupts(bool enable);
158
159 // Receiver/rx
160 uint32_t getRxAIDR();
161 uint32_t getRxStatusForChan(uint8_t chan);
162 void setCombinedRecvInterrupt(bool enable);
163 void enableClearChanInterrupt(uint8_t chan);
164 void disableClearChanInterrupt(uint8_t chan);
165};
166
167} // namespace Mailbox
168
169#endif /* #ifndef MHU_V2_HPP */