Jonny Svärd | ff265f9 | 2020-12-15 16:02:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /* Basic PL011 UART driver */ |
| 20 | |
| 21 | #include "uart_config.h" |
| 22 | #include "uart_stdout.h" |
| 23 | #include <stdint.h> |
| 24 | #include <stdio.h> |
| 25 | |
| 26 | #define CNTLQ 0x11 |
| 27 | #define CNTLS 0x13 |
| 28 | #define DEL 0x7F |
| 29 | #define BACKSPACE 0x08 |
| 30 | #define CR 0x0D |
| 31 | #define LF 0x0A |
| 32 | #define ESC 0x1B |
| 33 | |
| 34 | /*****************************************************************************/ |
| 35 | /* UART Control Register Locations */ |
| 36 | /*****************************************************************************/ |
| 37 | #define UART0_DR *((volatile uint32_t *)UART0_BASE) |
| 38 | #define UART0_RSR *((volatile uint32_t *)(UART0_BASE + 0x04)) |
| 39 | #define UART0_ECR *((volatile uint32_t *)(UART0_BASE + 0x04)) |
| 40 | #define UART0_LCRH *((volatile uint32_t *)(UART0_BASE + 0x2C)) |
| 41 | #define UART0_LCRM *((volatile uint32_t *)(UART0_BASE + 0x28)) |
| 42 | #define UART0_LCRL *((volatile uint32_t *)(UART0_BASE + 0x24)) |
| 43 | #define UART0_CR *((volatile uint32_t *)(UART0_BASE + 0x30)) |
| 44 | #define UART0_FR *((volatile uint32_t *)(UART0_BASE + 0x18)) |
| 45 | #define UART0_IIR *((volatile uint32_t *)(UART0_BASE + 0x1C)) |
| 46 | #define UART0_ICR *((volatile uint32_t *)(UART0_BASE + 0x44)) |
| 47 | |
| 48 | /*****************************************************************************/ |
| 49 | /* Received Status Register - RSR */ |
| 50 | /*****************************************************************************/ |
| 51 | #define RSR_OVERRUN_ERROR 0x08 |
| 52 | #define RSR_BREAK_ERROR 0x04 |
| 53 | #define RSR_PARITY_ERROR 0x02 |
| 54 | #define RSR_FRAMING_ERROR 0x01 |
| 55 | |
| 56 | /*****************************************************************************/ |
| 57 | /* Line Control High Byte Register - LCRH */ |
| 58 | /*****************************************************************************/ |
| 59 | #define LCRH_WORD_LENGTH_8 0x60 |
| 60 | #define LCRH_WORD_LENGTH_7 0x40 |
| 61 | #define LCRH_WORD_LENGTH_6 0x20 |
| 62 | #define LCRH_WORD_LENGTH_5 0x00 |
| 63 | #define LCRH_FIFO_ENABLED 0x10 |
| 64 | #define LCRH_2_STOP_BITS 0x08 |
| 65 | #define LCRH_EVEN_PARITY 0x04 |
| 66 | #define LCRH_PARITY_ENABLE 0x02 |
| 67 | #define LCRH_SEND_BREAK 0x01 |
| 68 | |
| 69 | /*****************************************************************************/ |
| 70 | /* Line Control Medium Byte Register - LCRM */ |
| 71 | /* This register specifies the high byte of the Baud rate divisor */ |
| 72 | /*****************************************************************************/ |
| 73 | #define LCRM_BAUD_460800 0x00 |
| 74 | #define LCRM_BAUD_230400 0x00 |
| 75 | #define LCRM_BAUD_115200 0x00 |
| 76 | #define LCRM_BAUD_76800 0x00 |
| 77 | #define LCRM_BAUD_57600 0x00 |
| 78 | #define LCRM_BAUD_38400 0x00 |
| 79 | #define LCRM_BAUD_19200 0x00 |
| 80 | #define LCRM_BAUD_14400 0x00 |
| 81 | #define LCRM_BAUD_9600 0x00 |
| 82 | #define LCRM_BAUD_2400 0x01 |
| 83 | #define LCRM_BAUD_1200 0x02 |
| 84 | |
| 85 | /*****************************************************************************/ |
| 86 | /* Line Control Low Byte Register - LCRL */ |
| 87 | /* This register specifies the low byte of the Baud rate divisor */ |
| 88 | /*****************************************************************************/ |
| 89 | #define LCRL_BAUD_460800 0x01 |
| 90 | #define LCRL_BAUD_230400 0x03 |
| 91 | #define LCRL_BAUD_115200 0x07 |
| 92 | #define LCRL_BAUD_76800 0x0B |
| 93 | #define LCRL_BAUD_57600 0x0F |
| 94 | #define LCRL_BAUD_38400 0xC |
| 95 | #define LCRL_BAUD_19200 0x2F |
| 96 | #define LCRL_BAUD_14400 0x3F |
| 97 | #define LCRL_BAUD_9600 0x5F |
| 98 | #define LCRL_BAUD_2400 0x7F |
| 99 | #define LCRL_BAUD_1200 0xFF |
| 100 | |
| 101 | /*****************************************************************************/ |
| 102 | /* Control Register - CR */ |
| 103 | /*****************************************************************************/ |
| 104 | #define CR_LOOP_BACK_EN 0x80 |
| 105 | #define CR_TIMEOUT_INT_EN 0x40 |
| 106 | #define CR_TX_INT_ENABLE 0x100 |
| 107 | #define CR_RX_INT_ENABLE 0x200 |
| 108 | #define CR_MODSTAT_INT_EN 0x08 |
| 109 | #define CR_UART_ENABLE 0x01 |
| 110 | |
| 111 | /*****************************************************************************/ |
| 112 | /* Flag Register - FR */ |
| 113 | /*****************************************************************************/ |
| 114 | #define FR_TX_FIFO_EMPTY 0x80 |
| 115 | #define FR_RX_FIFO_FULL 0x40 |
| 116 | #define FR_TX_FIFO_FULL 0x20 |
| 117 | #define FR_RX_FIFO_EMPTY 0x10 |
| 118 | #define FR_BUSY 0x08 |
| 119 | #define FR_CARRIER_DETECT 0x04 |
| 120 | #define FR_SET_READY 0x02 |
| 121 | #define FR_CLEAR_TO_SEND 0x01 |
| 122 | |
| 123 | /*****************************************************************************/ |
| 124 | /* Interrupt Identification Register - IIR */ |
| 125 | /*****************************************************************************/ |
| 126 | #define IIR_RX_TIME_OUT 0x08 |
| 127 | #define IIR_TX 0x04 |
| 128 | #define IIR_RX 0x02 |
| 129 | #define IIR_MODEM 0x01 |
| 130 | |
| 131 | void UartStdOutInit(void) { |
| 132 | // Disable the serial port while setting the baud rate and word length |
| 133 | UART0_CR = 0; |
| 134 | |
| 135 | // Clear the receive status register |
| 136 | UART0_ECR = 0; |
| 137 | |
| 138 | // Set the correct baud rate and word length |
| 139 | UART0_LCRL = LCRL_BAUD_115200; |
| 140 | UART0_LCRM = LCRM_BAUD_115200; |
| 141 | UART0_LCRH = LCRH_WORD_LENGTH_8; |
| 142 | |
| 143 | // Explicitly disable FIFO's for char mode |
| 144 | UART0_LCRH &= ~LCRH_FIFO_ENABLED; |
| 145 | |
| 146 | // Enable UART0 (and RX/TX) without interrupts |
| 147 | UART0_CR = CR_UART_ENABLE | CR_TX_INT_ENABLE | CR_RX_INT_ENABLE; |
| 148 | } |
| 149 | |
| 150 | unsigned char UartPutc(unsigned char ch) { |
| 151 | if (ch == '\n') { |
| 152 | (void)UartPutc('\r'); |
| 153 | } |
| 154 | while (UART0_FR & FR_TX_FIFO_FULL) |
| 155 | ; |
| 156 | UART0_DR = ch; |
| 157 | |
| 158 | return ch; |
| 159 | } |
| 160 | |
| 161 | unsigned char UartGetc(void) { |
| 162 | unsigned char c; |
| 163 | while (UART0_FR & FR_RX_FIFO_EMPTY) |
| 164 | ; |
| 165 | c = UART0_DR; |
| 166 | if (c == '\r') { |
| 167 | c = '\n'; |
| 168 | } |
| 169 | |
| 170 | return c; |
| 171 | } |
| 172 | |
| 173 | // Get line from terminal |
| 174 | unsigned int GetLine(char *lp, unsigned int len) { |
| 175 | unsigned int cnt = 0; |
| 176 | char c; |
| 177 | |
| 178 | do { |
| 179 | c = UartGetc(); |
| 180 | switch (c) { |
| 181 | case CNTLQ: /* ignore Control S/Q */ |
| 182 | case CNTLS: |
| 183 | break; |
| 184 | case BACKSPACE: |
| 185 | case DEL: |
| 186 | if (cnt == 0) { |
| 187 | break; |
| 188 | } |
| 189 | cnt--; /* decrement count */ |
| 190 | lp--; /* and line pointer */ |
| 191 | UartPutc(0x08); /* echo backspace */ |
| 192 | UartPutc(' '); |
| 193 | UartPutc(0x08); |
| 194 | fflush(stdout); |
| 195 | break; |
| 196 | case ESC: |
| 197 | case 0: |
| 198 | *lp = 0; /* ESC - stop editing line */ |
| 199 | return 0; |
| 200 | case CR: /* CR - done, stop editing line */ |
| 201 | *lp = c; |
| 202 | lp++; /* increment line pointer */ |
| 203 | cnt++; /* and count */ |
| 204 | c = LF; |
| 205 | UartPutc(*lp = c); /* echo and store character */ |
| 206 | fflush(stdout); |
| 207 | lp++; /* increment line pointer */ |
| 208 | cnt++; /* and count */ |
| 209 | break; |
| 210 | default: |
| 211 | UartPutc(*lp = c); /* echo and store character */ |
| 212 | fflush(stdout); |
| 213 | lp++; /* increment line pointer */ |
| 214 | cnt++; /* and count */ |
| 215 | break; |
| 216 | } |
| 217 | } while (cnt < len - 2 && c != LF); /* check limit and CR */ |
| 218 | *lp = 0; /* mark end of string */ |
| 219 | return 1; |
| 220 | } |