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Per Åstrand087ea212022-04-06 09:40:11 +02001/*
Mikael Olsson404a5362023-11-14 10:42:14 +01002 * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 * SPDX-License-Identifier: GPL-2.0-only
Per Åstrand087ea212022-04-06 09:40:11 +02004 *
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
8 * of such GNU licence.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, you can access it online at
17 * http://www.gnu.org/licenses/gpl-2.0.html.
Per Åstrand087ea212022-04-06 09:40:11 +020018 */
19
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26#include <linux/reset-controller.h>
27
28/* External system reset control bits */
29#define EXTSYS_CPU_WAIT (0x0)
30#define EXTSYS_RST_REQ (0x1)
31
32/* External system reset status bits */
33#define EXTSYS_STATUS_NO_RST_REQ (0x0)
34#define EXTSYS_STATUS_RST_REQ_NOT_COMPLETED (0x1)
35#define EXTSYS_STATUS_RST_REQ_COMPLETED (0x2)
36#define EXTSYS_STATUS_MASK(a) (0x3 & ((a) >> 1))
37
38struct cs1k_es_reset_data {
39 struct reset_controller_dev rcdev;
40 struct device *dev;
41 void __iomem *ctrl;
42 void __iomem *status;
43};
44
Mikael Olsson404a5362023-11-14 10:42:14 +010045static int cs1k_es_assert(struct reset_controller_dev *rcdev,
46 unsigned long id)
Per Åstrand087ea212022-04-06 09:40:11 +020047{
48 u32 status;
49 struct cs1k_es_reset_data *reset =
50 container_of(rcdev, struct cs1k_es_reset_data, rcdev);
51
52 if (id)
53 return -ENODEV;
54
55 dev_dbg(reset->dev, "Asserting reset");
56
57 /* set cpu wait and reset request of external system */
58 writel((1 << EXTSYS_CPU_WAIT) | (1 << EXTSYS_RST_REQ), reset->ctrl);
59
60 status = EXTSYS_STATUS_MASK(readl(reset->status));
61 dev_dbg(reset->dev, "status deasserting reset: %u", status);
62
63 return status == EXTSYS_STATUS_RST_REQ_COMPLETED ? 0 : 1;
64}
65
Mikael Olsson404a5362023-11-14 10:42:14 +010066static int cs1k_es_deassert(struct reset_controller_dev *rcdev,
67 unsigned long id)
Per Åstrand087ea212022-04-06 09:40:11 +020068{
69 u32 status;
70 struct cs1k_es_reset_data *reset =
71 container_of(rcdev, struct cs1k_es_reset_data, rcdev);
72
73 if (id)
74 return -ENODEV;
75
76 /* release cpu wait */
77 dev_dbg(reset->dev, "Deasserting reset");
78
79 writel(0, reset->ctrl);
80
81 status = EXTSYS_STATUS_MASK(readl(reset->status));
82 dev_dbg(reset->dev, "status deasserting reset: %u", status);
83
84 return status == EXTSYS_STATUS_NO_RST_REQ ? 0 : 1;
85}
86
87static struct reset_control_ops cs1k_es_reset_ops = {
88 .assert = cs1k_es_assert,
89 .deassert = cs1k_es_deassert,
90};
91
92static int of_reset_noop(struct reset_controller_dev *rcdev,
93 const struct of_phandle_args *reset_spec)
94{
95 return 0;
96}
97
98static int cs1k_es_reset_probe(struct platform_device *pdev)
99{
100 struct device *dev = &pdev->dev;
101 struct cs1k_es_reset_data *data;
102 struct resource *res;
103
104 if (!dev->of_node)
105 return -ENODEV;
106
107 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
108 if (!data)
109 return -ENOMEM;
110
111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rstreg");
112 data->ctrl = devm_ioremap_resource(dev, res);
113 if (IS_ERR(data->ctrl))
114 return PTR_ERR(data->ctrl);
115
116 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "streg");
117 data->status = devm_ioremap_resource(dev, res);
118 if (IS_ERR(data->status))
119 return PTR_ERR(data->status);
120
121 data->dev = dev;
122 platform_set_drvdata(pdev, data);
123
124 data->rcdev.owner = THIS_MODULE;
125 data->rcdev.nr_resets = 1;
126 data->rcdev.ops = &cs1k_es_reset_ops;
127 data->rcdev.of_node = pdev->dev.of_node;
128 /* only one reset line for this reset controller */
129 data->rcdev.of_xlate = of_reset_noop;
130
131 dev_info(dev, "registering reset to core");
132
133 return devm_reset_controller_register(dev, &data->rcdev);
134}
135
136static int cs1k_es_reset_remove(struct platform_device *pdev)
137{
138 return 0;
139}
140
141static const struct of_device_id cs1k_es_reset_match[] = {
142 { .compatible = "arm,cs1k_es_rst", .data = 0 },
143 { /* sentinel */ },
144};
145
146static struct platform_driver cs1k_es_reset_driver = {
147 .probe = cs1k_es_reset_probe,
148 .remove = cs1k_es_reset_remove,
149 .driver = {
150 .name = "cs1k_es-reset",
151 .of_match_table = of_match_ptr(cs1k_es_reset_match),
152 },
153};
154module_platform_driver(cs1k_es_reset_driver);
155
156MODULE_LICENSE("GPL v2");
157MODULE_DESCRIPTION("Arm Corstone1000 External System Reset Driver");
158MODULE_AUTHOR("Arm Ltd");