Per Åstrand | 087ea21 | 2022-04-06 09:40:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * This program is free software and is provided to you under the terms of the |
| 5 | * GNU General Public License version 2 as published by the Free Software |
| 6 | * Foundation, and any use by you of this program is subject to the terms |
| 7 | * of such GNU licence. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, you can access it online at |
| 16 | * http://www.gnu.org/licenses/gpl-2.0.html. |
| 17 | * |
| 18 | * SPDX-License-Identifier: GPL-2.0-only |
| 19 | */ |
| 20 | |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/of_device.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/reset-controller.h> |
| 28 | |
| 29 | /* External system reset control bits */ |
| 30 | #define EXTSYS_CPU_WAIT (0x0) |
| 31 | #define EXTSYS_RST_REQ (0x1) |
| 32 | |
| 33 | /* External system reset status bits */ |
| 34 | #define EXTSYS_STATUS_NO_RST_REQ (0x0) |
| 35 | #define EXTSYS_STATUS_RST_REQ_NOT_COMPLETED (0x1) |
| 36 | #define EXTSYS_STATUS_RST_REQ_COMPLETED (0x2) |
| 37 | #define EXTSYS_STATUS_MASK(a) (0x3 & ((a) >> 1)) |
| 38 | |
| 39 | struct cs1k_es_reset_data { |
| 40 | struct reset_controller_dev rcdev; |
| 41 | struct device *dev; |
| 42 | void __iomem *ctrl; |
| 43 | void __iomem *status; |
| 44 | }; |
| 45 | |
| 46 | int cs1k_es_assert(struct reset_controller_dev *rcdev, |
| 47 | unsigned long id) |
| 48 | { |
| 49 | u32 status; |
| 50 | struct cs1k_es_reset_data *reset = |
| 51 | container_of(rcdev, struct cs1k_es_reset_data, rcdev); |
| 52 | |
| 53 | if (id) |
| 54 | return -ENODEV; |
| 55 | |
| 56 | dev_dbg(reset->dev, "Asserting reset"); |
| 57 | |
| 58 | /* set cpu wait and reset request of external system */ |
| 59 | writel((1 << EXTSYS_CPU_WAIT) | (1 << EXTSYS_RST_REQ), reset->ctrl); |
| 60 | |
| 61 | status = EXTSYS_STATUS_MASK(readl(reset->status)); |
| 62 | dev_dbg(reset->dev, "status deasserting reset: %u", status); |
| 63 | |
| 64 | return status == EXTSYS_STATUS_RST_REQ_COMPLETED ? 0 : 1; |
| 65 | } |
| 66 | |
| 67 | int cs1k_es_deassert(struct reset_controller_dev *rcdev, |
| 68 | unsigned long id) |
| 69 | { |
| 70 | u32 status; |
| 71 | struct cs1k_es_reset_data *reset = |
| 72 | container_of(rcdev, struct cs1k_es_reset_data, rcdev); |
| 73 | |
| 74 | if (id) |
| 75 | return -ENODEV; |
| 76 | |
| 77 | /* release cpu wait */ |
| 78 | dev_dbg(reset->dev, "Deasserting reset"); |
| 79 | |
| 80 | writel(0, reset->ctrl); |
| 81 | |
| 82 | status = EXTSYS_STATUS_MASK(readl(reset->status)); |
| 83 | dev_dbg(reset->dev, "status deasserting reset: %u", status); |
| 84 | |
| 85 | return status == EXTSYS_STATUS_NO_RST_REQ ? 0 : 1; |
| 86 | } |
| 87 | |
| 88 | static struct reset_control_ops cs1k_es_reset_ops = { |
| 89 | .assert = cs1k_es_assert, |
| 90 | .deassert = cs1k_es_deassert, |
| 91 | }; |
| 92 | |
| 93 | static int of_reset_noop(struct reset_controller_dev *rcdev, |
| 94 | const struct of_phandle_args *reset_spec) |
| 95 | { |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static int cs1k_es_reset_probe(struct platform_device *pdev) |
| 100 | { |
| 101 | struct device *dev = &pdev->dev; |
| 102 | struct cs1k_es_reset_data *data; |
| 103 | struct resource *res; |
| 104 | |
| 105 | if (!dev->of_node) |
| 106 | return -ENODEV; |
| 107 | |
| 108 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
| 109 | if (!data) |
| 110 | return -ENOMEM; |
| 111 | |
| 112 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rstreg"); |
| 113 | data->ctrl = devm_ioremap_resource(dev, res); |
| 114 | if (IS_ERR(data->ctrl)) |
| 115 | return PTR_ERR(data->ctrl); |
| 116 | |
| 117 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "streg"); |
| 118 | data->status = devm_ioremap_resource(dev, res); |
| 119 | if (IS_ERR(data->status)) |
| 120 | return PTR_ERR(data->status); |
| 121 | |
| 122 | data->dev = dev; |
| 123 | platform_set_drvdata(pdev, data); |
| 124 | |
| 125 | data->rcdev.owner = THIS_MODULE; |
| 126 | data->rcdev.nr_resets = 1; |
| 127 | data->rcdev.ops = &cs1k_es_reset_ops; |
| 128 | data->rcdev.of_node = pdev->dev.of_node; |
| 129 | /* only one reset line for this reset controller */ |
| 130 | data->rcdev.of_xlate = of_reset_noop; |
| 131 | |
| 132 | dev_info(dev, "registering reset to core"); |
| 133 | |
| 134 | return devm_reset_controller_register(dev, &data->rcdev); |
| 135 | } |
| 136 | |
| 137 | static int cs1k_es_reset_remove(struct platform_device *pdev) |
| 138 | { |
| 139 | return 0; |
| 140 | } |
| 141 | |
| 142 | static const struct of_device_id cs1k_es_reset_match[] = { |
| 143 | { .compatible = "arm,cs1k_es_rst", .data = 0 }, |
| 144 | { /* sentinel */ }, |
| 145 | }; |
| 146 | |
| 147 | static struct platform_driver cs1k_es_reset_driver = { |
| 148 | .probe = cs1k_es_reset_probe, |
| 149 | .remove = cs1k_es_reset_remove, |
| 150 | .driver = { |
| 151 | .name = "cs1k_es-reset", |
| 152 | .of_match_table = of_match_ptr(cs1k_es_reset_match), |
| 153 | }, |
| 154 | }; |
| 155 | module_platform_driver(cs1k_es_reset_driver); |
| 156 | |
| 157 | MODULE_LICENSE("GPL v2"); |
| 158 | MODULE_DESCRIPTION("Arm Corstone1000 External System Reset Driver"); |
| 159 | MODULE_AUTHOR("Arm Ltd"); |