MLECO-2900: Update Cmake desc

Added QSPI_SRAM_BASE for Secure region.
Updated UART and other peripherals affected by change in reserved region
Updated names of some base addresses in cmake and template files
Error in TRM swapping individual for combined GPIO IRQs reported
Follow-up - Marked region in TRM not covered in CMake

Change-Id: I046e740053477fe3a51bc171a2b7e28f4a9f0523
Signed-off-by: Liam Barry <liam.barry@arm.com>
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
index 9382d4a..eec6fde 100644
--- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
+++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
@@ -52,6 +52,7 @@
 set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
 set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
 set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
+set(QSPI_SRAM_BASE_S      "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address")
 set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
 set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
 set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
@@ -88,16 +89,14 @@
 set(CMSDK_GPIO1_BASE      "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
 set(CMSDK_GPIO2_BASE      "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
 set(CMSDK_GPIO3_BASE      "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
-
-set(AHB_USER0_BASE        "0x41104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
-set(AHB_USER1_BASE        "0x41105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
-set(AHB_USER2_BASE        "0x41106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
-set(AHB_USER3_BASE        "0x41107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
-
-set(DMA0_BASE             "0x41200000" CACHE STRING "DMA0 (4KB)")
-set(DMA1_BASE             "0x41201000" CACHE STRING "DMA1 (4KB)")
-set(DMA2_BASE             "0x41202000" CACHE STRING "DMA2 (4KB)")
-set(DMA3_BASE             "0x41203000" CACHE STRING "DMA3 (4KB)")
+set(FMC_CMDSK_GPIO_BASE0  "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)")
+set(FMC_CMDSK_GPIO_BASE1  "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)")
+set(FMC_CMDSK_GPIO_BASE2  "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)")
+set(FMC_USER_AHB_BASE     "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)")
+set(DMA0_BASE             "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
+set(DMA1_BASE             "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
+set(DMA2_BASE             "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
+set(DMA3_BASE             "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
 
 set(SMSC9220_BASE         "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
 set(USB_BASE              "0x41500000" CACHE STRING "USB Base Address (1MB)")
@@ -154,10 +153,10 @@
 set(SEC_AHB_USER2_BASE     "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
 set(SEC_AHB_USER3_BASE     "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
 
-set(SEC_DMA0_BASE          "0x51200000" CACHE STRING "DMA0 (4KB)")
-set(SEC_DMA1_BASE          "0x51201000" CACHE STRING "DMA1 (4KB)")
-set(SEC_DMA2_BASE          "0x51202000" CACHE STRING "DMA2 (4KB)")
-set(SEC_DMA3_BASE          "0x51203000" CACHE STRING "DMA3 (4KB)")
+set(SEC_DMA0_BASE          "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
+set(SEC_DMA1_BASE          "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
+set(SEC_DMA2_BASE          "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
+set(SEC_DMA3_BASE          "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
 
 set(SEC_SMSC9220_BASE      "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
 set(SEC_USB_BASE           "0x51500000" CACHE STRING "USB Base Address (1MB)")
@@ -176,31 +175,29 @@
     set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
 endif (ETHOS_U_NPU_ENABLED)
 
-set(SEC_MPS3_I2C0_BASE     "0x58200000" CACHE STRING "Touch Screen I2C Base Address ")
-set(SEC_MPS3_I2C1_BASE     "0x58201000" CACHE STRING "Audio Interface I2C Base Address ")
-set(SEC_MPS3_SSP2_BASE     "0x58202000" CACHE STRING "ADC SPI PL022 Base Address")
-set(SEC_MPS3_SSP3_BASE     "0x58203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
-set(SEC_MPS3_SSP4_BASE     "0x58204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
-set(SEC_MPS3_I2C2_BASE     "0x58205000" CACHE STRING "Shield 0 SBCon Base Address ")
-set(SEC_MPS3_I2C3_BASE     "0x58206000" CACHE STRING "Shield 1 SBCon Base Address ")
+set(SEC_MPS3_I2C0_BASE     "0x59200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(SEC_MPS3_I2C1_BASE     "0x59201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(SEC_MPS3_SSP2_BASE     "0x59202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(SEC_MPS3_SSP3_BASE     "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+set(SEC_MPS3_SSP4_BASE     "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(SEC_MPS3_I2C2_BASE     "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(SEC_MPS3_I2C3_BASE     "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ")
+set(SEC_USER_APB_BASE      "0x59207000" CACHE STRING "User APB Base Address")
+set(SEC_MPS3_I2C5_BASE     "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
 
-set(SEC_USER_APB_BASE      "0x58207000" CACHE STRING "User APB Base Address")
-set(SEC_MPS3_I2C5_BASE     "0x58208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+set(SEC_MPS3_SCC_BASE         "0x59300000" CACHE STRING "SCC Base Address ")
+set(SEC_MPS3_AAIC_I2S_BASE    "0x59301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(SEC_MPS3_FPGAIO_BASE      "0x59302000" CACHE STRING "FPGA IO Base Address ")
 
-set(SEC_MPS3_SCC_BASE         "0x58300000" CACHE STRING "SCC Base Address ")
-set(SEC_MPS3_AAIC_I2S_BASE    "0x58301000" CACHE STRING "Audio Interface I2S Base Address ")
-set(SEC_MPS3_FPGAIO_BASE      "0x58302000" CACHE STRING "FPGA IO Base Address ")
+set(SEC_CMSDK_UART0_BASE      "0x59303000" CACHE STRING "UART 0 Base Address ")
+set(SEC_CMSDK_UART1_BASE      "0x59304000" CACHE STRING "UART 1 Base Address ")
+set(SEC_CMSDK_UART2_BASE      "0x59305000" CACHE STRING "UART 2 Base Address ")
+set(SEC_CMSDK_UART3_BASE      "0x59306000" CACHE STRING "UART 3 Base Address Shield 0")
+set(SEC_CMSDK_UART4_BASE      "0x59307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(SEC_CMSDK_UART5_BASE      "0x59308000" CACHE STRING "UART 5 Base Address ")
 
-set(SEC_CMSDK_UART0_BASE      "0x58303000" CACHE STRING "UART 0 Base Address ")
-set(SEC_CMSDK_UART1_BASE      "0x58304000" CACHE STRING "UART 1 Base Address ")
-set(SEC_CMSDK_UART2_BASE      "0x58305000" CACHE STRING "UART 2 Base Address ")
-set(SEC_CMSDK_UART3_BASE      "0x58306000" CACHE STRING "UART 3 Base Address Shield 0")
-set(SEC_CMSDK_UART4_BASE      "0x58307000" CACHE STRING "UART 4 Base Address Shield 1")
-set(SEC_CMSDK_UART5_BASE      "0x58308000" CACHE STRING "UART 5 Base Address ")
-
-set(SEC_CLCD_CONFIG_BASE      "0x5830A000" CACHE STRING "CLCD CONFIG Base Address ")
-set(SEC_RTC_BASE              "0x5830B000" CACHE STRING "RTC Base address ")
-
+set(SEC_CLCD_CONFIG_BASE      "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(SEC_RTC_BASE              "0x5930B000" CACHE STRING "RTC Base address ")
 
 ###################################################################################################
 #                                           MPCs                                                  #
@@ -216,10 +213,10 @@
 ###################################################################################################
 set(NONSEC_WATCHDOG_RESET_IRQn    " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
 set(NONSEC_WATCHDOG_IRQn          " 1" CACHE STRING " Non-Secure Watchdog Interrupt         ")
-set(S32K_TIMER_IRQn               " 2" CACHE STRING " S32K Timer Interrupt                  ")
+set(S32K_TIMER_IRQn               " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt          ")
 set(TIMER0_IRQn                   " 3" CACHE STRING " TIMER 0 Interrupt                     ")
 set(TIMER1_IRQn                   " 4" CACHE STRING " TIMER 1 Interrupt                     ")
-set(DUALTIMER_IRQn                " 5" CACHE STRING " Dual Timer Interrupt                  ")
+set(TIMER2_IRQn                   " 5" CACHE STRING " TIMER 2 Interrupt                     ")
 set(MPC_IRQn                      " 9" CACHE STRING " MPC Combined (Secure) Interrupt       ")
 set(PPC_IRQn                      "10" CACHE STRING " PPC Combined (Secure) Interrupt       ")
 set(MSC_IRQn                      "11" CACHE STRING " MSC Combined (Secure) Interrput       ")
@@ -232,7 +229,7 @@
 set(CPU0CTIIQ0_IRQn               "28" CACHE STRING " CPU0CTIIQ0" )
 set(CPU0CTIIQ01_IRQn              "29" CACHE STRING " CPU0CTIIQ01" )
 
-set(SYS_TSTAMP_COUNTER_IRQn       "32" CACHE STRING " System timestamp counter interrupt" )
+set(SYS_TSTAMP_COUNTER_IRQn       "32" CACHE STRING " System timestamp counter interrupt    ")
 set(UARTRX0_IRQn                  "33" CACHE STRING " UART 0 RX Interrupt                   ")
 set(UARTTX0_IRQn                  "34" CACHE STRING " UART 0 TX Interrupt                   ")
 set(UARTRX1_IRQn                  "35" CACHE STRING " UART 1 RX Interrupt                   ")
@@ -265,7 +262,6 @@
 set(GPIO1_IRQn                    "70" CACHE STRING " GPIO 1 Combined Interrupt             ")
 set(GPIO2_IRQn                    "71" CACHE STRING " GPIO 2 Combined Interrupt             ")
 set(GPIO3_IRQn                    "72" CACHE STRING " GPIO 3 Combined Interrupt             ")
-
 set(GPIO0_0_IRQn                  "73" CACHE STRING "")
 set(GPIO0_1_IRQn                  "74" CACHE STRING "")
 set(GPIO0_2_IRQn                  "75" CACHE STRING "")
diff --git a/scripts/cmake/templates/peripheral_irqs.h.template b/scripts/cmake/templates/peripheral_irqs.h.template
index 8e8888b..7696e13 100644
--- a/scripts/cmake/templates/peripheral_irqs.h.template
+++ b/scripts/cmake/templates/peripheral_irqs.h.template
@@ -32,7 +32,7 @@
 #cmakedefine S32K_TIMER_IRQn            (@S32K_TIMER_IRQn@)  /* S32K Timer Interrupt                  */
 #cmakedefine TIMER0_IRQn                (@TIMER0_IRQn@)  /* TIMER 0 Interrupt                     */
 #cmakedefine TIMER1_IRQn                (@TIMER1_IRQn@)  /* TIMER 1 Interrupt                     */
-#cmakedefine DUALTIMER_IRQn             (@DUALTIMER_IRQn@)  /* Dual Timer Interrupt                  */
+#cmakedefine TIMER2_IRQn                (@TIMER2_IRQn@)  /* TIMER 2 Interrupt                    */
 #cmakedefine MPC_IRQn                   (@MPC_IRQn@)  /* MPC Combined (@Secure@) Interrupt       */
 #cmakedefine PPC_IRQn                   (@PPC_IRQn@)  /* PPC Combined (@Secure@) Interrupt       */
 #cmakedefine MSC_IRQn                   (@MSC_IRQn@)  /* MSC Combined (@Secure@) Interrput       */
diff --git a/scripts/cmake/templates/peripheral_memmap.h.template b/scripts/cmake/templates/peripheral_memmap.h.template
index a8c883c..d7f0b3a 100644
--- a/scripts/cmake/templates/peripheral_memmap.h.template
+++ b/scripts/cmake/templates/peripheral_memmap.h.template
@@ -31,10 +31,10 @@
 #cmakedefine CMSDK_GPIO2_BASE         (@CMSDK_GPIO2_BASE@)       /* User GPIO 2 Base Address   */
 #cmakedefine CMSDK_GPIO3_BASE         (@CMSDK_GPIO3_BASE@)       /* User GPIO 3 Base Address   */
 
-#cmakedefine AHB_USER0_BASE           (@AHB_USER0_BASE@)       /* AHB USER 0 Base Address (4KB) */
-#cmakedefine AHB_USER1_BASE           (@AHB_USER1_BASE@)       /* AHB USER 1 Base Address (4KB)*/
-#cmakedefine AHB_USER2_BASE           (@AHB_USER2_BASE@)       /* AHB USER 2 Base Address (4KB)*/
-#cmakedefine AHB_USER3_BASE           (@AHB_USER3_BASE@)       /* AHB USER 3 Base Address (4KB)*/
+#cmakedefine FMC_CMDSK_GPIO_BASE0        (@FMC_CMDSK_GPIO_BASE0@)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
+#cmakedefine FMC_CMDSK_GPIO_BASE1        (@FMC_CMDSK_GPIO_BASE1@)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
+#cmakedefine FMC_CMDSK_GPIO_BASE2        (@FMC_CMDSK_GPIO_BASE2@)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
+#cmakedefine FMC_USER_AHB_BASE           (@FMC_USER_AHB_BASE@)          /* FMC_USER_AHB_BASE     Base Address (4KB)*/
 
 #cmakedefine DMA0_BASE                (@DMA0_BASE@)       /* DMA0 (4KB) */
 #cmakedefine DMA1_BASE                (@DMA1_BASE@)       /* DMA1 (4KB) */