MLECO-1886: fixed AXI related PMU counters, they show beats not cycle counts.
Updated profiling units and docs.
Change-Id: Iaa2913d2bd6b10eb99a5059e12bb9fdaec188192
diff --git a/docs/use_cases/ad.md b/docs/use_cases/ad.md
index 1ff9c4f..9014c96 100644
--- a/docs/use_cases/ad.md
+++ b/docs/use_cases/ad.md
@@ -450,9 +450,9 @@
Anomaly threshold is: -0.800000
Anomaly detected!
INFO - Profile for Inference:
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 628122
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 135087
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 62870
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 628122
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 135087
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 62870
INFO - NPU ACTIVE cycles: 1081007
INFO - NPU IDLE cycles: 626
INFO - NPU total cycles: 1081634
@@ -473,12 +473,12 @@
- 626 idle cycles: number of cycles for which the NPU was idle
- - 628,122 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 628,122 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 135,087 AXI0 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 135,087 AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus.
- - 62,870 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 62,870 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/docs/use_cases/asr.md b/docs/use_cases/asr.md
index 4600698..fa93d9a 100644
--- a/docs/use_cases/asr.md
+++ b/docs/use_cases/asr.md
@@ -496,9 +496,9 @@
INFO - For timestamp: 0.000000 (inference #: 1); label: e apartment by another door
INFO - Complete recognition: and he walked immediately out of the apartment by another door
INFO - Profile for Inference :
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 6564262
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 928889
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 841712
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 6564262
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 928889
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 841712
INFO - NPU ACTIVE cycles: 28450696
INFO - NPU IDLE cycles: 476
INFO - NPU total cycles: 28451172
@@ -517,12 +517,12 @@
- 476 idle cycles: number of cycles for which the NPU was idle
- - 6,564,262 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 6,564,262 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 928,889 AXI0 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 928,889 AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus.
- - 841,712 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 841,712 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/docs/use_cases/img_class.md b/docs/use_cases/img_class.md
index b26b746..9ba6d8c 100644
--- a/docs/use_cases/img_class.md
+++ b/docs/use_cases/img_class.md
@@ -422,9 +422,9 @@
INFO - 3) 458 (7.021370) -> bow tie, bow-tie, bowtie
INFO - 4) 288 (7.021370) -> lynx, catamount
INFO - Profile for Inference:
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 2489726
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 1098726
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 471129
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 2489726
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 1098726
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 471129
INFO - NPU ACTIVE cycles: 7489258
INFO - NPU IDLE cycles: 914
INFO - NPU total cycles: 7490172
@@ -445,12 +445,12 @@
- 914 idle cycles: number of cycles for which the NPU was idle
- - 2,489,726 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 2,489,726 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 1,098,726 AXI0 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 1,098,726 AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus.
- - 471,129 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 471,129 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/docs/use_cases/inference_runner.md b/docs/use_cases/inference_runner.md
index 350c1e8..06f02a4 100644
--- a/docs/use_cases/inference_runner.md
+++ b/docs/use_cases/inference_runner.md
@@ -280,9 +280,9 @@
```log
INFO - Final results:
INFO - Profile for Inference :
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 9332
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 3248
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 2219
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 9332
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 3248
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 2219
INFO - NPU ACTIVE cycles: 33145
INFO - NPU IDLE cycles: 1033
INFO - NPU total cycles: 34178
@@ -299,12 +299,12 @@
- 1,033 idle cycles: number of cycles for which the NPU was idle
- - 2,219 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 9,332 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 3,248 AXI0 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 3,248 AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus.
- - 9,332 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 2,219 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/docs/use_cases/kws.md b/docs/use_cases/kws.md
index 4942744..b1f0b26 100644
--- a/docs/use_cases/kws.md
+++ b/docs/use_cases/kws.md
@@ -453,9 +453,9 @@
INFO - Total number of inferences: 1
INFO - For timestamp: 0.000000 (inference #: 0); label: down, score: 0.996094; threshold: 0.900000
INFO - Profile for Inference:
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 217385
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 82607
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 59608
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 217385
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 82607
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 59608
INFO - NPU ACTIVE cycles: 680611
INFO - NPU IDLE cycles: 561
INFO - NPU total cycles: 681172
@@ -472,12 +472,12 @@
- 561 idle cycles: number of cycles for which the NPU was idle
- - 217,385 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 217,385 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 82,607 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 82,607 write cycles: The number of AXI beats with write transactions to AXI0 bus.
- - 59,608 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 59,608 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/docs/use_cases/kws_asr.md b/docs/use_cases/kws_asr.md
index 132a82d..bcb5ed1 100644
--- a/docs/use_cases/kws_asr.md
+++ b/docs/use_cases/kws_asr.md
@@ -549,9 +549,9 @@
INFO - For timestamp: 0.000000 (inference #: 0); threshold: 0.900000
INFO - label @ 0: yes, score: 0.996094
INFO - Profile for Inference:
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 217385
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 82607
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 59608
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 217385
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 82607
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 59608
INFO - NPU ACTIVE cycles: 680611
INFO - NPU IDLE cycles: 561
INFO - NPU total cycles: 681172
@@ -562,9 +562,9 @@
INFO - Result for inf 1: stoppe
INFO - Final result: no gow stoppe
INFO - Profile for Inference:
-INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED cycles: 13520864
-INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN cycles: 2841970
-INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED cycles: 2717670
+INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 13520864
+INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 2841970
+INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 2717670
INFO - NPU ACTIVE cycles: 28909309
INFO - NPU IDLE cycles: 863
INFO - NPU total cycles: 28910172
@@ -586,12 +586,12 @@
- 863 idle cycles: number of cycles for which the NPU was idle
- - 13,520,864 AXI0 read cycles: The number of cycles the NPU spends to execute AXI0 read transactions.
+ - 13,520,864 AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus.
AXI0 is the bus where Ethos-U55 NPU reads and writes to the computation buffers (activation buf/tensor arenas).
- - 2,841,970 AXI0 write cycles: The number of cycles the NPU spends to execute AXI0 write transactions.
+ - 2,841,970 AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus.
- - 2,717,670 AXI1 read cycles: The number of cycles the NPU spends to execute AXI1 read transactions.
+ - 2,717,670 AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus.
AXI1 is the bus where Ethos-U55 NPU reads the model (read only)
- For FPGA platforms, CPU cycle count can also be enabled. For FVP, however, CPU cycle counters should not be used as
diff --git a/source/application/main/Profiler.cc b/source/application/main/Profiler.cc
index ce59d9c..0456ba4 100644
--- a/source/application/main/Profiler.cc
+++ b/source/application/main/Profiler.cc
@@ -101,7 +101,7 @@
Statistics AXI0_RD {
.name = "NPU AXI0_RD_DATA_BEAT_RECEIVED",
- .unit = "cycles",
+ .unit = "beats",
.total = 0,
.avrg = 0.0,
.min = series[0].axi0writes,
@@ -109,7 +109,7 @@
};
Statistics AXI0_WR {
.name = "NPU AXI0_WR_DATA_BEAT_WRITTEN",
- .unit = "cycles",
+ .unit = "beats",
.total = 0,
.avrg = 0.0,
.min = series[0].axi0reads,
@@ -117,7 +117,7 @@
};
Statistics AXI1_RD {
.name = "NPU AXI1_RD_DATA_BEAT_RECEIVED",
- .unit = "cycles",
+ .unit = "beats",
.total = 0,
.avrg = 0.0,
.min = series[0].axi1reads,