| ; Copyright (c) 2021 Arm Limited. All rights reserved. |
| ; SPDX-License-Identifier: Apache-2.0 |
| ; |
| ; Licensed under the Apache License, Version 2.0 (the "License"); |
| ; you may not use this file except in compliance with the License. |
| ; You may obtain a copy of the License at |
| ; |
| ; http://www.apache.org/licenses/LICENSE-2.0 |
| ; |
| ; Unless required by applicable law or agreed to in writing, software |
| ; distributed under the License is distributed on an "AS IS" BASIS, |
| ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| ; See the License for the specific language governing permissions and |
| ; limitations under the License. |
| |
| ; ************************************************************* |
| ; *** Scatter-Loading Description File *** |
| ; ************************************************************* |
| ; Please see docs/sections/appendix.md for memory mapping information. |
| ; |
| ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| ; the model should only be placed in those regions. |
| ; |
| ;--------------------------------------------------------- |
| ; First load region (ITCM) |
| ;--------------------------------------------------------- |
| LOAD_REGION_0 0x00000000 0x00080000 |
| { |
| ;----------------------------------------------------- |
| ; First part of code mem - 512kiB |
| ;----------------------------------------------------- |
| itcm.bin 0x00000000 0x00080000 |
| { |
| *.o (RESET, +First) |
| * (InRoot$$Sections) |
| |
| ; Essentially only RO-CODE, RO-DATA is in a |
| ; different region. |
| .ANY (+RO) |
| } |
| |
| ;----------------------------------------------------- |
| ; 128kiB of 512kiB DTCM is used for any other RW or ZI |
| ; data. Note: this region is internal to the Cortex-M |
| ; CPU. |
| ;----------------------------------------------------- |
| dtcm.bin 0x20000000 0x00020000 |
| { |
| ; Any R/W and/or zero initialised data |
| .ANY(+RW +ZI) |
| } |
| |
| ;----------------------------------------------------- |
| ; 384kiB of stack space within the DTCM region. See |
| ; `dtcm.bin` for the first section. Note: by virtue of |
| ; being part of DTCM, this region is only accessible |
| ; from Cortex-M55. |
| ;----------------------------------------------------- |
| ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 |
| {} |
| |
| ;----------------------------------------------------- |
| ; SSE-300's internal SRAM of 4MiB - reserved for |
| ; activation buffers. |
| ; This region should have 3 cycle read latency from |
| ; both Cortex-M55 and Ethos-U NPU |
| ;----------------------------------------------------- |
| isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 |
| { |
| ; activation buffers a.k.a tensor arena |
| *.o (.bss.NoInit.activation_buf) |
| } |
| } |
| |
| ;--------------------------------------------------------- |
| ; Second load region (DDR) |
| ;--------------------------------------------------------- |
| LOAD_REGION_1 0x70000000 0x02000000 |
| { |
| ;----------------------------------------------------- |
| ; 32 MiB of DDR space for neural network model, |
| ; input vectors and labels. If the activation buffer |
| ; size required by the network is bigger than the |
| ; SRAM size available, it is accommodated here. |
| ;----------------------------------------------------- |
| ddr.bin 0x70000000 ALIGN 16 0x02000000 |
| { |
| ; nn model's baked in input matrices |
| *.o (ifm) |
| |
| ; nn model |
| *.o (nn_model) |
| |
| ; labels |
| *.o (labels) |
| |
| ; if the activation buffer (tensor arena) doesn't |
| ; fit in the SRAM region, we accommodate it here |
| *.o (activation_buf) |
| } |
| |
| ;----------------------------------------------------- |
| ; First 256kiB of BRAM (FPGA SRAM) used for RO data. |
| ; Note: Total BRAM size available is 2MiB. |
| ;----------------------------------------------------- |
| bram.bin 0x11000000 ALIGN 8 0x00040000 |
| { |
| ; RO data (incl. unwinding tables for debugging) |
| .ANY (+RO-DATA) |
| } |
| |
| ;----------------------------------------------------- |
| ; 960 KiB of remaining part of the 2MiB BRAM used as |
| ; heap space. 0x000F0000 of 0x0x001C0000 available. |
| ;----------------------------------------------------- |
| ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000F0000 |
| {} |
| } |