| Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | #ifndef ETHOS_U_NPU_MEM_CONFIG_H |
| 18 | #define ETHOS_U_NPU_MEM_CONFIG_H |
| 19 | |
| 20 | #define ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY 0 |
| 21 | #define ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM 1 |
| 22 | #define ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM 2 |
| 23 | |
| 24 | #define ETHOS_U_MEM_BYTE_ALIGNMENT 16 |
| 25 | |
| 26 | #ifndef ETHOS_U_NPU_MEMORY_MODE |
| 27 | #define ETHOS_U_NPU_MEMORY_MODE ETHOS_U_MEMORY_MODE_SHARED_SRAM |
| 28 | #endif /* ETHOS_U_NPU_MEMORY_MODE */ |
| 29 | |
| 30 | #if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM) |
| 31 | #define ETHOS_U_CACHE_BUF_SZ (393216U) /* See vela doc? for reference? */ |
| 32 | #else |
| 33 | #define ETHOS_U_CACHE_BUF_SZ (0U) |
| 34 | #endif /* CACHE_BUF_SZ */ |
| 35 | |
| 36 | /** |
| 37 | * Activation buffer aka tensor arena section name |
| 38 | * We have to place the tensor arena in different region based on the memory config. |
| 39 | **/ |
| 40 | #if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM) |
| 41 | #define ACTIVATION_BUF_SECTION section(".bss.NoInit.activation_buf_sram") |
| 42 | #define ACTIVATION_BUF_SECTION_NAME ("SRAM") |
| 43 | #elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY) |
| 44 | #define ACTIVATION_BUF_SECTION section(".bss.NoInit.activation_buf_sram") |
| 45 | #define ACTIVATION_BUF_SECTION_NAME ("SRAM") |
| 46 | #elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM) |
| 47 | #define ACTIVATION_BUF_SECTION section("activation_buf_dram") |
| 48 | #define CACHE_BUF_SECTION section(".bss.NoInit.ethos_u_cache") |
| 49 | #define ACTIVATION_BUF_SECTION_NAME ("DDR/DRAM") |
| 50 | #define CACHE_BUF_ATTRIBUTE __attribute__((aligned(ETHOS_U_MEM_BYTE_ALIGNMENT), CACHE_BUF_SECTION)) |
| 51 | #endif |
| 52 | |
| 53 | #endif /* ETHOS_U_NPU_MEM_CONFIG_H */ |