| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | // Auto-generated file |
| 18 | // ** DO NOT EDIT ** |
| 19 | |
| 20 | #ifndef PERIPHERAL_IRQS_H |
| 21 | #define PERIPHERAL_IRQS_H |
| 22 | |
| 23 | /******************************************************************************/ |
| 24 | /* Peripheral interrupt numbers */ |
| 25 | /******************************************************************************/ |
| 26 | |
| 27 | /* ------------------- Cortex-M Processor Exceptions Numbers -------------- */ |
| 28 | /* -14 to -1 should be defined by the system header */ |
| 29 | /* ---------------------- Core Specific Interrupt Numbers ------------------*/ |
| 30 | #cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@) /* Non-Secure Watchdog Reset Interrupt */ |
| 31 | #cmakedefine NONSEC_WATCHDOG_IRQn (@NONSEC_WATCHDOG_IRQn@) /* Non-Secure Watchdog Interrupt */ |
| 32 | #cmakedefine S32K_TIMER_IRQn (@S32K_TIMER_IRQn@) /* S32K Timer Interrupt */ |
| 33 | #cmakedefine TIMER0_IRQn (@TIMER0_IRQn@) /* TIMER 0 Interrupt */ |
| 34 | #cmakedefine TIMER1_IRQn (@TIMER1_IRQn@) /* TIMER 1 Interrupt */ |
| Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 35 | #cmakedefine TIMER2_IRQn (@TIMER2_IRQn@) /* TIMER 2 Interrupt */ |
| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 36 | #cmakedefine MPC_IRQn (@MPC_IRQn@) /* MPC Combined (@Secure@) Interrupt */ |
| 37 | #cmakedefine PPC_IRQn (@PPC_IRQn@) /* PPC Combined (@Secure@) Interrupt */ |
| 38 | #cmakedefine MSC_IRQn (@MSC_IRQn@) /* MSC Combined (@Secure@) Interrput */ |
| 39 | #cmakedefine BRIDGE_ERROR_IRQn (@BRIDGE_ERROR_IRQn@) /* Bridge Error Combined (@Secure@) Interrupt */ |
| 40 | #cmakedefine MGMT_PPU_IRQn (@MGMT_PPU_IRQn@) /* MGMT_PPU */ |
| 41 | #cmakedefine SYS_PPU_IRQn (@SYS_PPU_IRQn@) /* SYS_PPU */ |
| 42 | #cmakedefine CPU0_PPU_IRQn (@CPU0_PPU_IRQn@) /* CPU0_PPU */ |
| 43 | #cmakedefine DEBUG_PPU_IRQn (@DEBUG_PPU_IRQn@) /* DEBUG_PPU */ |
| 44 | #cmakedefine TIMER3_AON_IRQn (@TIMER3_AON_IRQn@) /* TIMER3_AON */ |
| 45 | #cmakedefine CPU0CTIIQ0_IRQn (@CPU0CTIIQ0_IRQn@) /* CPU0CTIIQ0 */ |
| 46 | #cmakedefine CPU0CTIIQ01_IRQn (@CPU0CTIIQ01_IRQn@) /* CPU0CTIIQ01 */ |
| 47 | |
| 48 | #cmakedefine SYS_TSTAMP_COUNTER_IRQn (@SYS_TSTAMP_COUNTER_IRQn@) /* System timestamp counter interrupt */ |
| 49 | |
| 50 | /* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */ |
| 51 | #cmakedefine UARTRX0_IRQn (@UARTRX0_IRQn@) /* UART 0 RX Interrupt */ |
| 52 | #cmakedefine UARTTX0_IRQn (@UARTTX0_IRQn@) /* UART 0 TX Interrupt */ |
| 53 | #cmakedefine UARTRX1_IRQn (@UARTRX1_IRQn@) /* UART 1 RX Interrupt */ |
| 54 | #cmakedefine UARTTX1_IRQn (@UARTTX1_IRQn@) /* UART 1 TX Interrupt */ |
| 55 | #cmakedefine UARTRX2_IRQn (@UARTRX2_IRQn@) /* UART 2 RX Interrupt */ |
| 56 | #cmakedefine UARTTX2_IRQn (@UARTTX2_IRQn@) /* UART 2 TX Interrupt */ |
| 57 | #cmakedefine UARTRX3_IRQn (@UARTRX3_IRQn@) /* UART 3 RX Interrupt */ |
| 58 | #cmakedefine UARTTX3_IRQn (@UARTTX3_IRQn@) /* UART 3 TX Interrupt */ |
| 59 | #cmakedefine UARTRX4_IRQn (@UARTRX4_IRQn@) /* UART 4 RX Interrupt */ |
| 60 | #cmakedefine UARTTX4_IRQn (@UARTTX4_IRQn@) /* UART 4 TX Interrupt */ |
| 61 | #cmakedefine UART0_IRQn (@UART0_IRQn@) /* UART 0 combined Interrupt */ |
| 62 | #cmakedefine UART1_IRQn (@UART1_IRQn@) /* UART 1 combined Interrupt */ |
| 63 | #cmakedefine UART2_IRQn (@UART2_IRQn@) /* UART 2 combined Interrupt */ |
| 64 | #cmakedefine UART3_IRQn (@UART3_IRQn@) /* UART 3 combined Interrupt */ |
| 65 | #cmakedefine UART4_IRQn (@UART4_IRQn@) /* UART 4 combined Interrupt */ |
| 66 | #cmakedefine UARTOVF_IRQn (@UARTOVF_IRQn@) /* UART 0,1,2,3 and 4 Overflow Interrupt */ |
| 67 | #cmakedefine ETHERNET_IRQn (@ETHERNET_IRQn@) /* Ethernet Interrupt */ |
| 68 | #cmakedefine I2S_IRQn (@I2S_IRQn@) /* I2S Interrupt */ |
| 69 | #cmakedefine TSC_IRQn (@TSC_IRQn@) /* Touch Screen Interrupt */ |
| 70 | #cmakedefine SPI2_IRQn (@SPI2_IRQn@) /* SPI 2 Interrupt */ |
| 71 | #cmakedefine SPI3_IRQn (@SPI3_IRQn@) /* SPI 3 Interrupt */ |
| 72 | #cmakedefine SPI4_IRQn (@SPI4_IRQn@) /* SPI 4 Interrupt */ |
| 73 | |
| 74 | #cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */ |
| 75 | |
| 76 | #cmakedefine GPIO0_IRQn (@GPIO0_IRQn@) /* GPIO 0 Combined Interrupt */ |
| 77 | #cmakedefine GPIO1_IRQn (@GPIO1_IRQn@) /* GPIO 1 Combined Interrupt */ |
| 78 | #cmakedefine GPIO2_IRQn (@GPIO2_IRQn@) /* GPIO 2 Combined Interrupt */ |
| 79 | #cmakedefine GPIO3_IRQn (@GPIO3_IRQn@) /* GPIO 3 Combined Interrupt */ |
| 80 | |
| 81 | #cmakedefine GPIO0_0_IRQn (@GPIO0_0_IRQn@) /* All P0 I/O pins used as irq source */ |
| 82 | #cmakedefine GPIO0_1_IRQn (@GPIO0_1_IRQn@) /* There are 16 pins in total */ |
| 83 | #cmakedefine GPIO0_2_IRQn (@GPIO0_2_IRQn@) |
| 84 | #cmakedefine GPIO0_3_IRQn (@GPIO0_3_IRQn@) |
| 85 | #cmakedefine GPIO0_4_IRQn (@GPIO0_4_IRQn@) |
| 86 | #cmakedefine GPIO0_5_IRQn (@GPIO0_5_IRQn@) |
| 87 | #cmakedefine GPIO0_6_IRQn (@GPIO0_6_IRQn@) |
| 88 | #cmakedefine GPIO0_7_IRQn (@GPIO0_7_IRQn@) |
| 89 | #cmakedefine GPIO0_8_IRQn (@GPIO0_8_IRQn@) |
| 90 | #cmakedefine GPIO0_9_IRQn (@GPIO0_9_IRQn@) |
| 91 | #cmakedefine GPIO0_10_IRQn (@GPIO0_10_IRQn@) |
| 92 | #cmakedefine GPIO0_11_IRQn (@GPIO0_11_IRQn@) |
| 93 | #cmakedefine GPIO0_12_IRQn (@GPIO0_12_IRQn@) |
| 94 | #cmakedefine GPIO0_13_IRQn (@GPIO0_13_IRQn@) |
| 95 | #cmakedefine GPIO0_14_IRQn (@GPIO0_14_IRQn@) |
| 96 | #cmakedefine GPIO0_15_IRQn (@GPIO0_15_IRQn@) |
| 97 | #cmakedefine GPIO1_0_IRQn (@GPIO1_0_IRQn@) /* All P1 I/O pins used as irq source */ |
| 98 | #cmakedefine GPIO1_1_IRQn (@GPIO1_1_IRQn@) /* There are 16 pins in total */ |
| 99 | #cmakedefine GPIO1_2_IRQn (@GPIO1_2_IRQn@) |
| 100 | #cmakedefine GPIO1_3_IRQn (@GPIO1_3_IRQn@) |
| 101 | #cmakedefine GPIO1_4_IRQn (@GPIO1_4_IRQn@) |
| 102 | #cmakedefine GPIO1_5_IRQn (@GPIO1_5_IRQn@) |
| 103 | #cmakedefine GPIO1_6_IRQn (@GPIO1_6_IRQn@) |
| 104 | #cmakedefine GPIO1_7_IRQn (@GPIO1_7_IRQn@) |
| 105 | #cmakedefine GPIO1_8_IRQn (@GPIO1_8_IRQn@) |
| 106 | #cmakedefine GPIO1_9_IRQn (@GPIO1_9_IRQn@) |
| 107 | #cmakedefine GPIO1_10_IRQn (@GPIO1_10_IRQn@) |
| 108 | #cmakedefine GPIO1_11_IRQn (@GPIO1_11_IRQn@) |
| 109 | #cmakedefine GPIO1_12_IRQn (@GPIO1_12_IRQn@) |
| 110 | #cmakedefine GPIO1_13_IRQn (@GPIO1_13_IRQn@) |
| 111 | #cmakedefine GPIO1_14_IRQn (@GPIO1_14_IRQn@) |
| 112 | #cmakedefine GPIO1_15_IRQn (@GPIO1_15_IRQn@) |
| 113 | #cmakedefine GPIO2_0_IRQn (@GPIO2_0_IRQn@) /* All P2 I/O pins used as irq source */ |
| 114 | #cmakedefine GPIO2_1_IRQn (@GPIO2_1_IRQn@) /* There are 15 pins in total */ |
| 115 | #cmakedefine GPIO2_2_IRQn (@GPIO2_2_IRQn@) |
| 116 | #cmakedefine GPIO2_3_IRQn (@GPIO2_3_IRQn@) |
| 117 | #cmakedefine GPIO2_4_IRQn (@GPIO2_4_IRQn@) |
| 118 | #cmakedefine GPIO2_5_IRQn (@GPIO2_5_IRQn@) |
| 119 | #cmakedefine GPIO2_6_IRQn (@GPIO2_6_IRQn@) |
| 120 | #cmakedefine GPIO2_7_IRQn (@GPIO2_7_IRQn@) |
| 121 | #cmakedefine GPIO2_8_IRQn (@GPIO2_8_IRQn@) |
| 122 | #cmakedefine GPIO2_9_IRQn (@GPIO2_9_IRQn@) |
| 123 | #cmakedefine GPIO2_10_IRQn (@GPIO2_10_IRQn@) |
| 124 | #cmakedefine GPIO2_11_IRQn (@GPIO2_11_IRQn@) |
| 125 | #cmakedefine GPIO2_12_IRQn (@GPIO2_12_IRQn@) |
| 126 | #cmakedefine GPIO2_13_IRQn (@GPIO2_13_IRQn@) |
| 127 | #cmakedefine GPIO2_14_IRQn (@GPIO2_14_IRQn@) |
| 128 | #cmakedefine GPIO2_15_IRQn (@GPIO2_15_IRQn@) |
| 129 | #cmakedefine GPIO3_0_IRQn (@GPIO3_0_IRQn@) /* All P3 I/O pins used as irq source */ |
| 130 | #cmakedefine GPIO3_1_IRQn (@GPIO3_1_IRQn@) /* There are 4 pins in total */ |
| 131 | #cmakedefine GPIO3_2_IRQn (@GPIO3_2_IRQn@) |
| 132 | #cmakedefine GPIO3_3_IRQn (@GPIO3_3_IRQn@) |
| 133 | #cmakedefine UARTRX5_IRQn (@UARTRX5_IRQn@) /* UART 5 RX Interrupt */ |
| 134 | #cmakedefine UARTTX5_IRQn (@UARTTX5_IRQn@) /* UART 5 TX Interrupt */ |
| 135 | #cmakedefine UART5_IRQn (@UART5_IRQn@) /* UART 5 combined Interrupt */ |
| 136 | #cmakedefine HDCLCD_IRQn (@HDCLCD_IRQn@) /* HDCLCD Interrupt */ |
| 137 | |
| 138 | #endif /* PERIPHERAL_IRQS_H */ |