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review.mlplatform.org / ml / ethos-u / ml-embedded-evaluation-kit / 31ae9f09bb3535975595e999fbc7baca889e46e8 / . / source / hal / platform / mps3 / include / smm_mps3.h
blob: 1c0e0f295304fcaeb4d6e9e434a3f8341e7e8fee [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]1/*
2 * Copyright (c) 2021 Arm Limited. All rights reserved.
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#ifndef SMM_MPS3_H
18#define SMM_MPS3_H
19
20#include "cmsis.h" /* Device specific header file. */
21#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
22
23#if defined ( __CC_ARM )
24#pragma anon_unions
25#endif
26
27/******************************************************************************/
28/* FPGA System Register declaration */
29/******************************************************************************/
30
31typedef struct
32{
33 __IO uint32_t LED; /* Offset: 0x000 (R/W) LED connections
34 * [31:2] : Reserved
35 * [1:0] : LEDs
36 */
37 uint32_t RESERVED1[1];
38 __IO uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
39 * [31:2] : Reserved
40 * [1:0] : Buttons
41 */
42 uint32_t RESERVED2[1];
43 __IO uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
44 __IO uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
45 __IO uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
46 * Increments when 32-bit prescale counter reach zero
47 */
48 __IO uint32_t PRESCALE; /* Offset: 0x01C (R/W) Prescaler
49 * Bit[31:0] : reload value for prescale counter
50 */
51 __IO uint32_t PSCNTR; /* Offset: 0x020 (R/W) 32-bit Prescale counter
52 * current value of the pre-scaler counter
53 * The Cycle Up Counter increment when the prescale down counter reach 0
54 * The pre-scaler counter is reloaded with PRESCALE after reaching 0.
55 */
56 uint32_t RESERVED3[1];
57 __IO uint32_t SWITCHES; /* Offset: 0x028 (R/W) Switches
58 * [31:8] : Reserved
59 * [7:0] : Switches
60 */
61 uint32_t RESERVED4[8];
62 __IO uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
63 * [31:10] : Reserved
64 * [9] :
65 * [8] :
66 * [7] : ADC_SPI_nCS
67 * [6] : CLCD_BL_CTRL
68 * [5] : CLCD_RD
69 * [4] : CLCD_RS
70 * [3] : CLCD_RESET
71 * [2] : SHIELD_1_SPI_nCS
72 * [1] : SHIELD_0_SPI_nCS
73 * [0] : CLCD_CS
74 */
75} MPS3_FPGAIO_TypeDef;
76
77/* MISC register bit definitions. */
78
79#define CLCD_CS_Pos 0
80#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
81#define SHIELD_0_nCS_Pos 1
82#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
83#define SHIELD_1_nCS_Pos 2
84#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
85#define CLCD_RESET_Pos 3
86#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
87#define CLCD_RS_Pos 4
88#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
89#define CLCD_RD_Pos 5
90#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
91#define CLCD_BL_Pos 6
92#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
93#define ADC_nCS_Pos 7
94#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
95
96/******************************************************************************/
97/* SCC Register declaration */
98/******************************************************************************/
99
100typedef struct
101{
102 __IO uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to ZBT
103 * [31:1] : Reserved
104 * [0] 1 : REMAP BlockRam to ZBT
105 */
106 __IO uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user LEDs
107 * [31:8] : Reserved
108 * [7:0] : MCC LEDs
109 */
110 uint32_t RESERVED0[1];
111 __I uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
112 * [31:8] : Reserved
113 * [7:0] : These bits indicate state of the MCC switches
114 */
115 __I uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board revision
116 * [31:4] : Reserved
117 * [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
118 */
119 __I uint32_t CFG_ACLK; /* Offset: 0x014 (R/ ) System Clock
120 */
121 uint32_t RESERVED1[34];
122 __IO uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
123 * [31:0] : Data
124 */
125 __IO uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data register
126 * [31:0] : Data
127 */
128 __IO uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
129 * [31] : Start (generates interrupt on write to this bit)
130 * [30] : R/W access
131 * [29:26] : Reserved
132 * [25:20] : Function value
133 * [19:12] : Reserved
134 * [11:0] : Device (value of 0/1/2 for supported clocks)
135 */
136 __IO uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status information
137 * [31:2] : Reserved
138 * [1] : Error
139 * [0] : Complete
140 */
141 __IO uint32_t RESERVED2[20];
142 __IO uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
143 * [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
144 * [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
145 * [15:1] : Reserved
146 * [0] : This bit indicates if all enabled DLLs are locked
147 */
148 uint32_t RESERVED3[957];
149 __I uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
150 * [31:24] : FPGA build number
151 * [23:20] : V2M-MPS3 target board revision (A = 0, B = 1)
152 * [19:11] : Reserved
153 * [10] : if “1” SCC_SW register has been implemented
154 * [9] : if “1” SCC_LED register has been implemented
155 * [8] : if “1” DLL lock register has been implemented
156 * [7:0] : number of SCC configuration register
157 */
158 __I uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains information about the FPGA image
159 * [31:24] : Implementer ID: 0x41 = ARM
160 * [23:20] : Application note IP variant number
161 * [19:16] : IP Architecture: 0x4 =AHB
162 * [15:4] : Primary part number: 386 = AN386
163 * [3:0] : Application note IP revision number
164 */
165} MPS3_SCC_TypeDef;
166
167
168/******************************************************************************/
169/* SSP Peripheral declaration */
170/******************************************************************************/
171
172typedef struct
173{
174 __IO uint32_t CR0; /* Offset: 0x000 (R/W) Control register 0
175 * [31:16] : Reserved
176 * [15:8] : Serial clock rate
177 * [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
178 * [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
179 * [5:4] : Frame format
180 * [3:0] : Data Size Select
181 */
182 __IO uint32_t CR1; /* Offset: 0x004 (R/W) Control register 1
183 * [31:4] : Reserved
184 * [3] : Slave-mode output disable
185 * [2] : Master or slave mode select
186 * [1] : Synchronous serial port enable
187 * [0] : Loop back mode
188 */
189 __IO uint32_t DR; /* Offset: 0x008 (R/W) Data register
190 * [31:16] : Reserved
191 * [15:0] : Transmit/Receive FIFO
192 */
193 __I uint32_t SR; /* Offset: 0x00C (R/ ) Status register
194 * [31:5] : Reserved
195 * [4] : PrimeCell SSP busy flag
196 * [3] : Receive FIFO full
197 * [2] : Receive FIFO not empty
198 * [1] : Transmit FIFO not full
199 * [0] : Transmit FIFO empty
200 */
201 __IO uint32_t CPSR; /* Offset: 0x010 (R/W) Clock prescale register
202 * [31:8] : Reserved
203 * [8:0] : Clock prescale divisor
204 */
205 __IO uint32_t IMSC; /* Offset: 0x014 (R/W) Interrupt mask set or clear register
206 * [31:4] : Reserved
207 * [3] : Transmit FIFO interrupt mask
208 * [2] : Receive FIFO interrupt mask
209 * [1] : Receive timeout interrupt mask
210 * [0] : Receive overrun interrupt mask
211 */
212 __I uint32_t RIS; /* Offset: 0x018 (R/ ) Raw interrupt status register
213 * [31:4] : Reserved
214 * [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
215 * [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
216 * [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
217 * [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
218 */
219 __I uint32_t MIS; /* Offset: 0x01C (R/ ) Masked interrupt status register
220 * [31:4] : Reserved
221 * [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
222 * [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
223 * [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
224 * [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
225 */
226 __O uint32_t ICR; /* Offset: 0x020 ( /W) Interrupt clear register
227 * [31:2] : Reserved
228 * [1] : Clears the SSPRTINTR interrupt
229 * [0] : Clears the SSPRORINTR interrupt
230 */
231 __IO uint32_t DMACR; /* Offset: 0x024 (R/W) DMA control register
232 * [31:2] : Reserved
233 * [1] : Transmit DMA Enable
234 * [0] : Receive DMA Enable
235 */
236} MPS3_SSP_TypeDef;
237
238
239/* SSP_CR0 Control register 0. */
240#define SSP_CR0_DSS_Pos 0 /* Data Size Select. */
241#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
242#define SSP_CR0_FRF_Pos 4 /* Frame Format Select. */
243#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
244#define SSP_CR0_SPO_Pos 6 /* SSPCLKOUT polarity. */
245#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
246#define SSP_CR0_SPH_Pos 7 /* SSPCLKOUT phase. */
247#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
248#define SSP_CR0_SCR_Pos 8 /* Serial Clock Rate (divide). */
249#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
250
251#define SSP_CR0_SCR_DFLT 0x0300 /* Serial Clock Rate (divide), default set at 3. */
252#define SSP_CR0_FRF_MOT 0x0000 /* Frame format. */
253#define SSP_CR0_DSS_8 0x0007 /* Data packet size, 8bits. */
254#define SSP_CR0_DSS_16 0x000F /* Data packet size, 16bits. */
255
256/* SSP_CR1 Control register 1. */
257#define SSP_CR1_LBM_Pos 0 /* Loop Back Mode. */
258#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
259#define SSP_CR1_SSE_Pos 1 /* Serial port enable. */
260#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
261#define SSP_CR1_MS_Pos 2 /* Master or Slave mode. */
262#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
263#define SSP_CR1_SOD_Pos 3 /* Slave Output mode Disable. */
264#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
265
266/* SSP_SR Status register. */
267#define SSP_SR_TFE_Pos 0 /* Transmit FIFO empty. */
268#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
269#define SSP_SR_TNF_Pos 1 /* Transmit FIFO not full. */
270#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
271#define SSP_SR_RNE_Pos 2 /* Receive FIFO not empty. */
272#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
273#define SSP_SR_RFF_Pos 3 /* Receive FIFO full. */
274#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
275#define SSP_SR_BSY_Pos 4 /* Busy. */
276#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
277
278/* SSP_CPSR Clock prescale register. */
279#define SSP_CPSR_CPD_Pos 0 /* Clock prescale divisor. */
280#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
281
282#define SSP_CPSR_DFLT 0x0008 /* Clock prescale (use with SCR), default set at 8. */
283
284/* SSPIMSC Interrupt mask set and clear register. */
285#define SSP_IMSC_RORIM_Pos 0 /* Receive overrun not Masked. */
286#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
287#define SSP_IMSC_RTIM_Pos 1 /* Receive timeout not Masked. */
288#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
289#define SSP_IMSC_RXIM_Pos 2 /* Receive FIFO not Masked. */
290#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
291#define SSP_IMSC_TXIM_Pos 3 /* Transmit FIFO not Masked. */
292#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
293
294/* SSPRIS Raw interrupt status register. */
295#define SSP_RIS_RORRIS_Pos 0 /* Raw Overrun interrupt flag. */
296#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
297#define SSP_RIS_RTRIS_Pos 1 /* Raw Timemout interrupt flag. */
298#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
299#define SSP_RIS_RXRIS_Pos 2 /* Raw Receive interrupt flag. */
300#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
301#define SSP_RIS_TXRIS_Pos 3 /* Raw Transmit interrupt flag. */
302#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
303
304/* SSPMIS Masked interrupt status register. */
305#define SSP_MIS_RORMIS_Pos 0 /* Masked Overrun interrupt flag. */
306#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
307#define SSP_MIS_RTMIS_Pos 1 /* Masked Timemout interrupt flag. */
308#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
309#define SSP_MIS_RXMIS_Pos 2 /* Masked Receive interrupt flag. */
310#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
311#define SSP_MIS_TXMIS_Pos 3 /* Masked Transmit interrupt flag. */
312#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
313
314/* SSPICR Interrupt clear register. */
315#define SSP_ICR_RORIC_Pos 0 /* Clears Overrun interrupt flag. */
316#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
317#define SSP_ICR_RTIC_Pos 1 /* Clears Timemout interrupt flag. */
318#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
319
320/* SSPDMACR DMA control register. */
321#define SSP_DMACR_RXDMAE_Pos 0 /* Enable Receive FIFO DMA. */
322#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
323#define SSP_DMACR_TXDMAE_Pos 1 /* Enable Transmit FIFO DMA. */
324#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
325
326/******************************************************************************/
327/* Audio and Touch Screen (I2C) Peripheral declaration */
328/******************************************************************************/
329
330typedef struct
331{
332 union {
333 __O uint32_t CONTROLS; /* Offset: 0x000 CONTROL Set Register ( /W). */
334 __I uint32_t CONTROL; /* Offset: 0x000 CONTROL Status Register (R/ ). */
335 };
336 __O uint32_t CONTROLC; /* Offset: 0x004 CONTROL Clear Register ( /W). */
337} MPS3_I2C_TypeDef;
338
339#define SDA 1 << 1
340#define SCL 1 << 0
341
342
343/******************************************************************************/
344/* Audio I2S Peripheral declaration */
345/******************************************************************************/
346
347typedef struct
348{
349 /*!< Offset: 0x000 CONTROL Register (R/W) */
350 __IO uint32_t CONTROL; /* <h> CONTROL </h>
351 * <o.0> TX Enable
352 * <0=> TX disabled
353 * <1=> TX enabled
354 * <o.1> TX IRQ Enable
355 * <0=> TX IRQ disabled
356 * <1=> TX IRQ enabled
357 * <o.2> RX Enable
358 * <0=> RX disabled
359 * <1=> RX enabled
360 * <o.3> RX IRQ Enable
361 * <0=> RX IRQ disabled
362 * <1=> RX IRQ enabled
363 * <o.10..8> TX Buffer Water Level
364 * <0=> / IRQ triggers when any space available
365 * <1=> / IRQ triggers when more than 1 space available
366 * <2=> / IRQ triggers when more than 2 space available
367 * <3=> / IRQ triggers when more than 3 space available
368 * <4=> Undefined!
369 * <5=> Undefined!
370 * <6=> Undefined!
371 * <7=> Undefined!
372 * <o.14..12> RX Buffer Water Level
373 * <0=> Undefined!
374 * <1=> / IRQ triggers when less than 1 space available
375 * <2=> / IRQ triggers when less than 2 space available
376 * <3=> / IRQ triggers when less than 3 space available
377 * <4=> / IRQ triggers when less than 4 space available
378 * <5=> Undefined!
379 * <6=> Undefined!
380 * <7=> Undefined!
381 * <o.16> FIFO reset
382 * <0=> Normal operation
383 * <1=> FIFO reset
384 * <o.17> Audio Codec reset
385 * <0=> Normal operation
386 * <1=> Assert audio Codec reset
387 */
388 /*!< Offset: 0x004 STATUS Register (R/ ) */
389 __I uint32_t STATUS; /* <h> STATUS </h>
390 * <o.0> TX Buffer alert
391 * <0=> TX buffer don't need service yet
392 * <1=> TX buffer need service
393 * <o.1> RX Buffer alert
394 * <0=> RX buffer don't need service yet
395 * <1=> RX buffer need service
396 * <o.2> TX Buffer Empty
397 * <0=> TX buffer have data
398 * <1=> TX buffer empty
399 * <o.3> TX Buffer Full
400 * <0=> TX buffer not full
401 * <1=> TX buffer full
402 * <o.4> RX Buffer Empty
403 * <0=> RX buffer have data
404 * <1=> RX buffer empty
405 * <o.5> RX Buffer Full
406 * <0=> RX buffer not full
407 * <1=> RX buffer full
408 */
409 union {
410 /*!< Offset: 0x008 Error Status Register (R/ ) */
411 __I uint32_t ERROR; /* <h> ERROR </h>
412 * <o.0> TX error
413 * <0=> Okay
414 * <1=> TX overrun/underrun
415 * <o.1> RX error
416 * <0=> Okay
417 * <1=> RX overrun/underrun
418 */
419 /*!< Offset: 0x008 Error Clear Register ( /W) */
420 __O uint32_t ERRORCLR; /* <h> ERRORCLR </h>
421 * <o.0> TX error
422 * <0=> Okay
423 * <1=> Clear TX error
424 * <o.1> RX error
425 * <0=> Okay
426 * <1=> Clear RX error
427 */
428 };
429 /*!< Offset: 0x00C Divide ratio Register (R/W) */
430 __IO uint32_t DIVIDE; /* <h> Divide ratio for Left/Right clock </h>
431 * <o.9..0> TX error (default 0x80)
432 */
433 /*!< Offset: 0x010 Transmit Buffer ( /W) */
434 __O uint32_t TXBUF; /* <h> Transmit buffer </h>
435 * <o.15..0> Right channel
436 * <o.31..16> Left channel
437 */
438
439 /*!< Offset: 0x014 Receive Buffer (R/ ) */
440 __I uint32_t RXBUF; /* <h> Receive buffer </h>
441 * <o.15..0> Right channel
442 * <o.31..16> Left channel
443 */
444 uint32_t RESERVED1[186];
445 __IO uint32_t ITCR; /* <h> Integration Test Control Register </h>
446 * <o.0> ITEN
447 * <0=> Normal operation
448 * <1=> Integration Test mode enable
449 */
450 __O uint32_t ITIP1; /* <h> Integration Test Input Register 1</h>
451 * <o.0> SDIN
452 */
453 __O uint32_t ITOP1; /* <h> Integration Test Output Register 1</h>
454 * <o.0> SDOUT
455 * <o.1> SCLK
456 * <o.2> LRCK
457 * <o.3> IRQOUT
458 */
459} MPS3_I2S_TypeDef;
460
461#define I2S_CONTROL_TXEN_Pos 0
462#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
463
464#define I2S_CONTROL_TXIRQEN_Pos 1
465#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
466
467#define I2S_CONTROL_RXEN_Pos 2
468#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
469
470#define I2S_CONTROL_RXIRQEN_Pos 3
471#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
472
473#define I2S_CONTROL_TXWLVL_Pos 8
474#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
475
476#define I2S_CONTROL_RXWLVL_Pos 12
477#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
478/* FIFO reset. */
479#define I2S_CONTROL_FIFORST_Pos 16
480#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
481/* Codec reset. */
482#define I2S_CONTROL_CODECRST_Pos 17
483#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
484
485#define I2S_STATUS_TXIRQ_Pos 0
486#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
487
488#define I2S_STATUS_RXIRQ_Pos 1
489#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
490
491#define I2S_STATUS_TXEmpty_Pos 2
492#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
493
494#define I2S_STATUS_TXFull_Pos 3
495#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
496
497#define I2S_STATUS_RXEmpty_Pos 4
498#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
499
500#define I2S_STATUS_RXFull_Pos 5
501#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
502
503#define I2S_ERROR_TXERR_Pos 0
504#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
505
506#define I2S_ERROR_RXERR_Pos 1
507#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
508
509/******************************************************************************/
510/* SMSC9220 Register Definitions */
511/******************************************************************************/
512
513typedef struct /* SMSC LAN9220 */
514{
515__I uint32_t RX_DATA_PORT; /* Receive FIFO Ports (offset 0x0). */
516 uint32_t RESERVED1[0x7];
517__O uint32_t TX_DATA_PORT; /* Transmit FIFO Ports (offset 0x20). */
518 uint32_t RESERVED2[0x7];
519
520__I uint32_t RX_STAT_PORT; /* Receive FIFO status port (offset 0x40). */
521__I uint32_t RX_STAT_PEEK; /* Receive FIFO status peek (offset 0x44). */
522__I uint32_t TX_STAT_PORT; /* Transmit FIFO status port (offset 0x48). */
523__I uint32_t TX_STAT_PEEK; /* Transmit FIFO status peek (offset 0x4C). */
524
525__I uint32_t ID_REV; /* Chip ID and Revision (offset 0x50). */
526__IO uint32_t IRQ_CFG; /* Main Interrupt Configuration (offset 0x54). */
527__IO uint32_t INT_STS; /* Interrupt Status (offset 0x58). */
528__IO uint32_t INT_EN; /* Interrupt Enable Register (offset 0x5C). */
529 uint32_t RESERVED3; /* Reserved for future use (offset 0x60). */
530__I uint32_t BYTE_TEST; /* Read-only byte order testing register 87654321h (offset 0x64). */
531__IO uint32_t FIFO_INT; /* FIFO Level Interrupts (offset 0x68). */
532__IO uint32_t RX_CFG; /* Receive Configuration (offset 0x6C). */
533__IO uint32_t TX_CFG; /* Transmit Configuration (offset 0x70). */
534__IO uint32_t HW_CFG; /* Hardware Configuration (offset 0x74). */
535__IO uint32_t RX_DP_CTL; /* RX Datapath Control (offset 0x78). */
536__I uint32_t RX_FIFO_INF; /* Receive FIFO Information (offset 0x7C). */
537__I uint32_t TX_FIFO_INF; /* Transmit FIFO Information (offset 0x80). */
538__IO uint32_t PMT_CTRL; /* Power Management Control (offset 0x84). */
539__IO uint32_t GPIO_CFG; /* General Purpose IO Configuration (offset 0x88). */
540__IO uint32_t GPT_CFG; /* General Purpose Timer Configuration (offset 0x8C). */
541__I uint32_t GPT_CNT; /* General Purpose Timer Count (offset 0x90). */
542 uint32_t RESERVED4; /* Reserved for future use (offset 0x94). */
543__IO uint32_t ENDIAN; /* WORD SWAP Register (offset 0x98). */
544__I uint32_t FREE_RUN; /* Free Run Counter (offset 0x9C). */
545__I uint32_t RX_DROP; /* RX Dropped Frames Counter (offset 0xA0). */
546__IO uint32_t MAC_CSR_CMD; /* MAC CSR Synchronizer Command (offset 0xA4). */
547__IO uint32_t MAC_CSR_DATA; /* MAC CSR Synchronizer Data (offset 0xA8). */
548__IO uint32_t AFC_CFG; /* Automatic Flow Control Configuration (offset 0xAC). */
549__IO uint32_t E2P_CMD; /* EEPROM Command (offset 0xB0). */
550__IO uint32_t E2P_DATA; /* EEPROM Data (offset 0xB4). */
551
552} SMSC9220_TypeDef;
553
554/* SMSC9220 MAC Registers Indices. */
555#define SMSC9220_MAC_CR 0x1
556#define SMSC9220_MAC_ADDRH 0x2
557#define SMSC9220_MAC_ADDRL 0x3
558#define SMSC9220_MAC_HASHH 0x4
559#define SMSC9220_MAC_HASHL 0x5
560#define SMSC9220_MAC_MII_ACC 0x6
561#define SMSC9220_MAC_MII_DATA 0x7
562#define SMSC9220_MAC_FLOW 0x8
563#define SMSC9220_MAC_VLAN1 0x9
564#define SMSC9220_MAC_VLAN2 0xA
565#define SMSC9220_MAC_WUFF 0xB
566#define SMSC9220_MAC_WUCSR 0xC
567
568/* SMSC9220 PHY Registers Indices. */
569#define SMSC9220_PHY_BCONTROL 0x0
570#define SMSC9220_PHY_BSTATUS 0x1
571#define SMSC9220_PHY_ID1 0x2
572#define SMSC9220_PHY_ID2 0x3
573#define SMSC9220_PHY_ANEG_ADV 0x4
574#define SMSC9220_PHY_ANEG_LPA 0x5
575#define SMSC9220_PHY_ANEG_EXP 0x6
576#define SMSC9220_PHY_MCONTROL 0x17
577#define SMSC9220_PHY_MSTATUS 0x18
578#define SMSC9220_PHY_CSINDICATE 0x27
579#define SMSC9220_PHY_INTSRC 0x29
580#define SMSC9220_PHY_INTMASK 0x30
581#define SMSC9220_PHY_CS 0x31
582
583/******************************************************************************/
584/* Peripheral declaration */
585/******************************************************************************/
586
587#define MPS3_TS_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C0_BASE )
588#define MPS3_AAIC_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C1_BASE )
589#define MPS3_CAM_I2C2 ((MPS3_I2C_TypeDef *) MPS3_I2C2_BASE )
590#define MPS3_CAM_I2C3 ((MPS3_I2C_TypeDef *) MPS3_I2C3_BASE )
591#define MPS3_AAIC_I2S ((MPS3_I2S_TypeDef *) MPS3_AAIC_I2S_BASE )
592#define MPS3_FPGAIO ((MPS3_FPGAIO_TypeDef *) MPS3_FPGAIO_BASE )
593#define MPS3_SCC ((MPS3_SCC_TypeDef *) MPS3_SCC_BASE )
594#define MPS3_SSP0 ((MPS3_SSP_TypeDef *) MPS3_SSP0_BASE )
595#define MPS3_SSP1 ((MPS3_SSP_TypeDef *) MPS3_SSP1_BASE )
596#define MPS3_SSP2 ((MPS3_SSP_TypeDef *) MPS3_SSP2_BASE )
597#define MPS3_SSP3 ((MPS3_SSP_TypeDef *) MPS3_SSP3_BASE )
598#define MPS3_SSP4 ((MPS3_SSP_TypeDef *) MPS3_SSP4_BASE )
599#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE)
600
601/******************************************************************************/
602/* Secure Peripheral declaration */
603/******************************************************************************/
604
605#define SEC_TS_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C0_BASE )
606#define SEC_AAIC_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C1_BASE )
607#define SEC_AAIC_I2S ((MPS3_I2S_TypeDef *) SEC_MPS3_AAIC_I2S_BASE )
608#define SEC_FPGAIO ((MPS3_FPGAIO_TypeDef *) SEC_MPS3_FPGAIO_BASE )
609#define SEC_SCC ((MPS3_SCC_TypeDef *) SEC_MPS3_SCC_BASE )
610#define SEC_SSP0 ((MPS3_SSP_TypeDef *) SEC_SSP0_BASE )
611#define SEC_SSP1 ((MPS3_SSP_TypeDef *) SEC_SSP1_BASE )
612#define SEC_SSP2 ((MPS3_SSP_TypeDef *) SEC_MPS3_SSP2_BASE )
613#define SEC_SMSC9220 ((SMSC9220_TypeDef *) SEC_SMSC9220_BASE)
614
615#endif /* SMM_MPS3_H */