blob: fcd18be8b10f617408bcf9cad8e31248e985ccc3 [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001;
2; Copyright (c) 2021 Arm Limited. All rights reserved.
3; SPDX-License-Identifier: Apache-2.0
4;
5; Licensed under the Apache License, Version 2.0 (the "License");
6; you may not use this file except in compliance with the License.
7; You may obtain a copy of the License at
8;
9; http://www.apache.org/licenses/LICENSE-2.0
10;
11; Unless required by applicable law or agreed to in writing, software
12; distributed under the License is distributed on an "AS IS" BASIS,
13; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14; See the License for the specific language governing permissions and
15; limitations under the License.
16;
17
18; -----------------------------------------------------------------------------
19; Vela configuration file
20
21; -----------------------------------------------------------------------------
22; System Configuration
23
24; Ethos-U55 Deep Embedded: SRAM (1.6 GB/s) and Flash (0.1 GB/s)
25[System_Config.Ethos_U55_Deep_Embedded]
26core_clock=200e6
27axi0_port=Sram
28axi1_port=OffChipFlash
29Sram_clock_scale=1.0
30Sram_burst_length=32
31Sram_read_latency=32
32Sram_write_latency=32
33OffChipFlash_clock_scale=0.0625
34OffChipFlash_burst_length=128
35OffChipFlash_read_latency=64
36OffChipFlash_write_latency=64
37
38; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s)
39[System_Config.Ethos_U55_High_End_Embedded]
40core_clock=500e6
41axi0_port=Sram
42axi1_port=OffChipFlash
43Sram_clock_scale=1.0
44Sram_burst_length=32
45Sram_read_latency=32
46Sram_write_latency=32
47OffChipFlash_clock_scale=0.125
48OffChipFlash_burst_length=128
49OffChipFlash_read_latency=64
50OffChipFlash_write_latency=64
51
52; -----------------------------------------------------------------------------
53; Memory Mode
54
55; SRAM Only: only one AXI port is used and the SRAM is used for all storage
56[Memory_Mode.Sram_Only]
57const_mem_area=Axi0
58arena_mem_area=Axi0
59cache_mem_area=Axi0
60
61; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
62; The non-SRAM memory is assumed to be read-only
63[Memory_Mode.Shared_Sram]
64const_mem_area=Axi1
65arena_mem_area=Axi0
66cache_mem_area=Axi0
67
68; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U
69; The non-SRAM memory is assumed to be read-writeable
70[Memory_Mode.Dedicated_Sram]
71const_mem_area=Axi1
72arena_mem_area=Axi1
73cache_mem_area=Axi0
74cache_sram_size=393216
75
76; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U
77; The non-SRAM memory is assumed to be read-writeable
78[Memory_Mode.Dedicated_Sram_512KB]
79inherit=Memory_Mode.Dedicated_Sram
80cache_sram_size=524288